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driving DO lines with external clock wired to PFI lines

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Hi all,

 

I have few issues understanding how to use hardware timing resources in M series USB6229, with particular focus on DO. I have read last couple of day all google offered on the subject but I am still straggling with some basic tasks. To cut the story short, the 1e6 dollar question:  can I set up 7 independent DO lines where (different tasks or virtual channels) where lines use same hardware timing source (eg, freqout or CO0 set to ~10kHz sampling time routed to PFI0).

Note: the reason I need 7 independent lines and not a port output (which would be obvious solution) is because I need to have (vastly) different number of samples and for each line.

 

Follow up question regarding timing: As I understood, any of PFI ports could be used and a input to the external clock which could be used to drive DO line(s) samples. I have tried to generate one DO, eg. P0\line4 by using CO0 to generate 10kHz sample rate.  The signal on the line4 is pulse with frequency of few Hz which I routed to PF6 (with actual wire) in hope to use this signal as a clock for line5. I tried this but I am receiving errors about "resources in use"

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Possible reason(s):

Specified route cannot be satisfied, because it requires resources that are currently in use by another route.

Property: SampClk.Src
Property: SampClk.ActiveEdge
Source Device: USB-6229
Source Terminal: PFI6

Required Resources in Use by
Task Name: _unnamedTask<7B>
Source Device: USB-6229
Source Terminal: PFI4
Destination Device: USB-6229
Destination Terminal: do/SampleClock

Task Name: _unnamedTask<79>

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 Apparently, many of internal clocks are routed internally to different PFI lines which mean the lines are occupied resource, and I do not know how to solve this.

I wanted to ask you does this principle sound as something that should work and if you know about some examples that would be excellent.   

 

Any help would be greatly appreciated.

Cheers, Nenad

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Hi Nenad_Mijatovic, 

                                    I was wondering if you are still experiencing issues if so could you specify the exact error code you are receiving?

                                    I look forward to hearing from you.

 

Kind regards

Seb

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Hi,

 

Pretty much, yes. Basically I would benefit great deal if I could drive few DOs with supplying external CLC that I generated by few DOs.

 

Any help would be appreciated.

 

Kind regards,

Nenad

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> To cut the story short, the 1e6 dollar question:  can I set up 7 independent DO lines where (different tasks or virtual channels) where lines use same hardware timing source (eg, freqout or CO0 set to ~10kHz sampling time routed to PFI0).

 

No, you can't. The USB-6229 has a single digital output FIFO which can only be used by one task at a time.

 

> Note: the reason I need 7 independent lines and not a port output (which would be obvious solution) is because I need to have (vastly) different number of samples and for each line.

 

It should be possible to generate all seven signals with a single task by generating a waveform that includes all seven signals. If the signals repeat at different rates or you need to start/stop them independently, you will have to disable regeneration and continuously generate new waveform segments on the fly. Continuous Write Digital Port - External Clock - Non Regeneration should be a good starting point for the DAQmx programming, but actually generating the data is likely to be the challenging part.

 

Brad

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Brad Keryan
NI R&D
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Hi Brad,

 

Thanks! I got a feeling that  might be too good to be true. Coudl you tell me where coudl I find the information about numebrs of FIFO?

 

Kind regards,

Nenad

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Hi Nenad,

 

The DO FIFO specs are in the NI 622x Specifications: "Waveform generation (DO) FIFO ... 2,047 samples". Also, even if the device had more than one DO FIFO, it wouldn't support seven fully-independent streams: "USB Signal Stream (USB devices) ... 4, can be used for analog input, analog output, digital input, digital output, counter/timer 0, counter/timer 1".

 

Since you want to use the same sample clock for all seven lines, it is possible to generate the signals you want to generate, but you must design your application to combine them before writing them to the device. Start with the example I linked and try to replace the waveform generation logic with your own. If you're generating all of the signals from a single instance of a single VI, this should be pretty straightforward. If you need multiple VIs or multiple instances of the same VI to generate signals, consider using a queue to send signals to the data generation loop.

 

Brad

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Brad Keryan
NI R&D
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