cRIO & NI 9403 DIO module jitter

[demo66]

Hello!

The 9403 module is specificated with an update time of  7us. I reach the time only when I have only 1 while loop. If I have more loops parallel, then the update time without jitter is about 70us.

I want to realize PWM in- and outputs, for this feature I have made seperate loops. I also have a data player. Therefore I put values from the FPGA RAM with variable time differences out.

Does all IO pins need to be in the same loop to reach the 7us?

Thank you for your help.

[Christian Mergl]

Hey!

Yes you have to put all in one loop using one node to update all values within the specified 7µs.

Christian