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buffered loopback test

HI All,

 

I developed simple buffered loopback test DIO test vi using NI PCI 6536, VI is working fine without issues.but, Output data often is not same as input data.

though, same VI is working fine with PCI DIO 32HS and i am able to see expected output.

 

I am using Port 0& 2 for loopback Test, On board clock is the source of the timing synchronization.

 

Attached is the Vi which i had created using labview Version 2011.

 

Please give me suggestions/solutions as soon as possible. your help is highly appericiated.

 

 

Thanks

Durai S

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Does the input seem to be delayed by a few samples to the output?  Or is the input just totallly different?


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output is not delayed or entirely different.....

Output data is misplaced with respect into input data......

 

Please see the screen shot attached for more information.

 

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No, it is delayed by exactly one sample.  I kind of expected this.


So it appears that the clock starting on the falling edge when you start up your two tasks.  Try switching which clock edges your inputs and outputs happen with.


GCentral
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Hi,

 

I tried switching the clock edges of sample clock. i am seeing better results.but, there is misplacing data happening once for approximately every 20 times.

 

for Digital Output  :- Falling edge is selected. likewise, For digital Input  :- Rising Edge.

 

Is this intermittent issue dependent with PC or Device(DAQ Hardware)?

 

 

Thanks

Durai S

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Hi, 

 

it appears like output data is also dependent on sampling frequency. it we changes the frequency, misplacing of data is happening many times.

 

Please let me know your inputs on this.....

 

 

Thanks

Durai S

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What all circuitry do you have between your inputs and outputs?

 

This is likely just a case of propagation delay, which can't really be helped.  So it makes sense that the faster you sample, the more of these delayed readings you will see.


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Message 7 of 10
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I dont have any circuitry in between input and output, it is direct connection (one to one)

 

How to reduce propagation delay that you mentioned?

 

Thanks

Durai S

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In addition to that, If I increase sampling frequency, output data is entirely different with respect to input data.....

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Can anybody help me on this issue?

 

Please tell me whether it can be done or not. If it is possible, Please give me simple clear example.

 

 

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