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What is the maximum update rate for PCI-6509

What is the maximum update rate for PCI-6509. What is the main constraint (hardware) for obtaining maximum speed? Smiley Indifferent
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Hi SETj!

   I posted a similar question....

   The answer is: there's not a fixed update rate that can be granted, because NI 6509 update values "as fast as possible", this means that it depends on system architecture (motherboard / processor speed, thread priority...).  Moreover, you cannot rely on "sample clock", which doesn't exist on this board. 

   Of course, the fastest sample rate you can obtain is with "vectorial" read/write, that is you define a task in which you generate/read a fixed number of samples (say 1000).  With this technique, I sampled/generated bits spaced of 5 microseconds, while with perform "scalar" read/write functions, I reached about 25 microseconds spacing.  Of course, these values depends on the features I mentioned abve.

   An example of scalar read:
 
     DAQmxReadDigitalU8(   , ..., <samples per channel = 1> , ...);
     DAQmxReadDigitalU8(   , ..., <samples per channel = 1> , ...);
     DAQmxReadDigitalU8(   , ..., <samples per channel = 1> , ...);

   etc...

 An example of vectorial read:

   DAQmxReadDigitalU8(   , ..., <samples per channel = 1000> , ...);

   Hope it helps, let me know!

graziano

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Hi SETj,

For more information on this issue, please see Software-Timed Digital I/O Benchmarks with DAQmx. This KB has links to some benchmarking results for different 65xx DIO boards.  It also has the actual benchmarking program attached.  You can use this program to test your own system.

Hope this helps!

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Thanks guys. This information is very helpful.
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