Using both Driver and Comparator on PXI-6552 cards to test for DUT Tristate

[broke]

As a functiona test, I need to verify that my DUT outputs are tristate at a certain point in time.

Is it possible to use the Generation pin electronics driver to drive a mid-range voltage (say 1.6V) and have the Acquisition pin electronics window comparator look for voltage significantly away from this level (Vil = 1.4V and Vih = 1.8V)?

The problem so far is that the WDT waveform format only allows a single alias per pin and there are no aliases that indicate DRIVE and COMPARE both.

Perhaps I need to set some HSDIO attributes that manually turn the drivers on, and then check for invalid (between Vil and Vih) data during the cycles when the DUT is tristate?

[Raajit_Lall]

Hi Broke,

This is definitely an interesting use case of the 6552.  You can definitely set it to output and input in the format that you want.

>>> The problem so far is that the WDT waveform format only allows a single alias per pin and there are no aliases that indicate DRIVE and COMPARE both.

Could you please elaborate on your problem above.  The 6552 is capable of outputting and reading on adjacent edges.  The best method for you to create drive and compare data on the same pin would be to use the Digital Waveform Editor.  You can select which sample you want as output and which one you want as input.  If you do not have the Digital Waveform Editor (you can download an evaluation version here), you can also use LabVIEW to create these waveforms.

In LabVIEW, to create data with output and compare data you can use the Build Digital Data VI.  In this VI the input array "data" can have upto 7 values.

0 - 0 (Force Down)

1 - 1 (Force Up)

2 - Z (Force Off)

3 - L

4 - H

5 - X

6 - T (Compare Off)

7 - V (Compare Valid)

This information is available in the LabVIEW help file.

By using the above combination you can create digital data with both output and input (compare) values.  Once you do this, you can use a generation and an acquisition session to generate and acquire your data.  A good example is in the Example Finder (Hardware Input and Output >> Modular Instruments >> NI-HSDIO >> Dynamic Generation and Acquisition ).  The Dynamic Generation and Acquisition Demo.vi should serve the purpose.

Hope that answers your question.  Let me know if you have any other questions.

You should also take a look at this white paper that talks about capabilities of the 6552 which are similar to your requirements.

Testing Protection/Clamp Diodes with the NI 655X Digital Waveform Generator/Analyzer

Message Edited by Raajit L on 02-24-2009 03:52 PM

[broke]

Thank you very much for your reply Raajit.

I am aware of the bi-directional capability of the 6652 pin electronics (and am taking advantage of this).

>>> The 6552 is capable of outputting and reading on adjacent edges.

However, what I need is the 6652 to output and read on THE SAME edge / cycle.  I need to driver to stay ON (driving logic "1" which I will set to 1.6V) while the comparator is checking for a "V" valid result.  I cannot input both the "1" and "V" aliases into my waveform in the same cycle.

Are you suggesting that if I drive a "...1V..." pattern (Force Up, followed by Compare Valid) that the driver will remain in the "Force Up" state while the "Compare Valid" cycle occurs?  I don't think this is the case as it would require the use of a "Z" (Force Off) cycle BETWEEN all force and receive cycles for bi-directional testing, and I know this isn't required.
 
>>> Testing Protection/Clamp Diodes with the NI 655X Digital Waveform Generator/Analyzer

This paper is very close to what I need to do, but as you know this paper describes a setup using Static sessions.  I must use Dynamic sessions, because I must present an elaborate pattern on the input and control signals of my DUT in order to yield the Tristate DUT condition which I must then check.

I know that I cannot have BOTH a dynamic generation and static generation session configured for my card simultaneously.  I think what I might need to do is:

1. Setup and execute my conditioning patterns with a Dynamic Generation session.
2. The last state for the Tristate pins in this dynamic pattern will be "1" (Force Up)
3. Close this Dynamic Session (and hope that all drive pins do not change states)

Now, implement the procedures in the Continuity Test white paper:

4. Start a Static Generation and Static Acquisition session. (on just the pins under test)
5. Configure the drive high voltage to 1.6V
7. Write static xFF (which it should already be doing... but this might force the vih change)
8. Read static result and compare for a "V" result

Will the closing the Dynamic session and Initializing the Static sessions upset the state of the drivers for all the pins NOT included in the Static sessions (but are included in the Dynamic sessions).  (There are DUT control signals that must be maintained in order for the static acquisition to be valid.)

Thank you,

Brian

[JuanCarlos · Accepted solution]

Hi Brian,

Unfortunatelly the 6552 does not support "drive and verify" states. Everytime the pin compares it goes into tristate. Possibly the best workaround would be to fetch the acquired data and check the state of the pin at that particular sample. In this case you set your waveform to drive a value and the acquisition will be acquiring what you are driving (or what's left of the signal). This may be problematic if you are running complex scripts, since it's hard to figure out where in the waveforma is that particular state, but electrically the measurement will be correct. 

Let me know if you have any further questions on this workaround.

Regards,

Juan Carlos

[broke]

Juan Carlos,

>>> Unfortunatelly the 6552 does not support "drive and verify" states. Everytime the pin compares it goes into tristate.

You are specifically referring to Dynamic Generation and Acquisition?  The "Continuity Test" white paper implies that both Drive and Compare can be simultaneously enabled in Static sessions.

I believe your solution of Fetching acquired data while driving the DUT's tristate pins will work for me.  I don't know why I did not think of this.  If the DUT is counter-driving the pin, I should see some variance away from either a system driven "1" or "0" (depending upon the state that the DUT is stuck in) because of the 50ohm output impedance of the pin driver in the 6552.... as long as I set my comparator thresholds close enough to the driver force voltages (since the DUT probably won't have a BUNCH of drive current to force a voltage difference across the 6552's 50ohm resistor).

I will code this test up now and reply on how it works.

[broke]

I now have a Tristate test that works:

1) Create a dynamic pattern that sets up the DUT outputs so they are tristate, then DRIVE those DUT outputs with Logic "0" for several cycles.

2) Set the Drive levels to nominal settings, but set the Compare levels: Vol = Vil + 100mV and Voh = Vil + 150mV

3) Run the pattern and when finished download a record capturing the "tristate" cycles

4) These should all measure logic LOW (as they are being driven low by the 6552's drivers)

5) If one of the pins is stuck high, it will push enough current back into the 6552 driver's 50ohm output impedance to hopefully shift the voltage past Voh and register logic HIGH

Then, repeat the whole process by driving a logic "1" during the tristate cycles, with Voh = Vih - 100mV and Vol = Vih - 150mV

I still would like to understand 2 things:

1) Juan Carlos said "Unfortunatelly the 6552 does not support "drive and verify" states. Everytime the pin compares it goes into tristate."  But, the Continuity (diode check) white paper indicates that drive and compare is possible simultaneously in Static mode...  why not Dynamic mode?

2) If I play with my Voh and Vol levels too much, I will upset the trigger signal synchronization that I am exporting and monitoring on PFI0 (Generation session exports a marker0 to PFI0 and my Acquisition session uses PFI0 as both the Start Trigger and the Advance Trigger).  How "safe" is it to set Voh and Vol so close (within 100mV) of Vih or Vil... Am I at risk of losing trigger pulses?

[JuanCarlos]

Brian,

By "Unfortunatelly the 6552 does not support "drive and verify" states" I meant for hardware compare operations. You can run a dynamic/static generation and acuiqisiton in the same pin at the same time, but there is no state in a hardware compare waveform that allows you to drive and compare in the same clock cycle. 

As far as your second question, the 6552 specs show a voltage accuracy of +-20 mV on generation and +-30 mV in acquisition. Base on this numbers, if you keep the voltage away at least 50 mV you should not have any problems. Keep in mind that this will be affected by any external connection in the PFI. I would probably recommend to test this and see how close you can get without any failures. 

I hope this helps,

Juan Carlos

[broke]

>>> You can run a dynamic/static generation and acuiqisiton in the same pin at the same time, but there is no state in a hardware compare waveform that allows you to drive and compare in the same clock cycle.

Thank you for your explanation.

It is unfortunately that I cannot create a HWC waveform that can utilize the driver's as a high speed termination for a 50ohm DUT.  It sounds like I will ALWAYS have to Fetch a record and do the logic comparison in the PC if I want to keep the drivers active as 50ohm terminations for my DUT lines.

Any chance the FPGA could be modified to enable simultaneous Drive and HWC?  It would require more aliases, but you definitely have the bits to use up.  The current alias set only uses up 3 of 8 bits per pin per cycle.