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Upper/Lower limits of PWM Frequency

Hello together,

 

I am planning to control a DC-motor with the PWM-Output of a Microcontroller and I am not sure how to set the PWM-Frequency. The microcontroller update rate is 200Hz and the DC-motor time constant can be calculated from L/R. But how can I calculate the duty cycle frequency and the counts per cycle frequency (percentage resolution)?

Is it a problem, when the circuit current does not reach is steady value during a PWM-period? Because if the duty cycle frequency is very high, then for short ON-Times, the steady value will not be achieved, right?

 Also the counts-per-cycle frequency specifies what the timing resolution will be (for example 1000 counts per duty cycle, means that barely 2^10 bits can be achieved), if I am right

How exactly do I calculate the upper and lower limits?

 

Thank you in advance

Lysandris



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Hello Lysandros89,

 

what NI hardware do you want to use, because if using DAQmx you can direct put out a frequency and change this during the execution.

What exactly should be generated from our hardware and what options do you want to change?

best regards
Alexander
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Thank you for the response.

I would use CompactRio as a real-time target for the system dynamics and a Raspberry PI as the controller. The Raspberry is generating control signals at 200Hz and sends them to the target computer. Lets suppose that the model runs at 1000Hz, in order to capture the whole bandwidth of the system dynamics.

 

In this case, since the CompactRio would run on a higher rate, each PWM cycle serves five target cycles, right? Is it reasonable to use the same ON-OFF pair every five consecutive model cycles, or should I copy it into five smaller cycles so that the input signals changes at 1000Hz as the model itself?

 

During operation I only want to change physical model parameters and not the control characteristics.



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Hello Lysandros89,


it is always better to run the detection faster so you can better anylse the measured signal. If you now want to calculate the duty cylce of the 200 Hz signal and you only use 1000 hz for the acquisiton you have only five steps this means the error can be round about 20%.

 


With cRIO and the FPGA you can faster aquire the signal so the duty cycle can be better calculated. With a rate of 20 KHz the error is round about 1%.

 

 

When running both acquire and measure with the same rate it can happen that a signal is not detected if the edges from the PWM are very close together.

best regards
Alexander
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