11-30-2022 01:04 PM
The high-level block diagram in the PXIe-657x training manual shows relays on the channels between the pin electronics and the VHDCI connector. I have a situation where two PXI resources have to access the same bond pad of a die at mutually exclusive periods and I am trying to determine the impedance of the DIO channel where leakage might occur.
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11-30-2022 08:34 PM
Those are going to be solid-state relays and there will be leakage. I would recommend adding an external relay in your test setup to completely isolate the signals.
12-01-2022 08:55 AM
Thank you, santo_13 for a very quick response to my query. A design oversight uses the same bond pad in one set of test structures to be driven by the PXIe-6570 as the enable pin and on another set of structures that pad sources a 125nA current reference to be connected to a PXIe-4071 DMM in the automated wafer probing system. A few nanoamps of leakage is significant so your suggestion for an external relay is the only real option.