I'm trying to continuously generate digital pattern through scripting. The pattern will be generated whenever there's rising edge in PFI. The code works fine but there's about 360 ns generation delay with respect to rising edge in PFI. Is there a way to get rid of this delay? I've attached here the code I'm using, appreciate any feedback
Looking at page 35 of the spec sheet of the PXIe-6556, it looks like there is a maximum delay between receiving a trigger and beginning generation of 6*(sample clock period) + 600 ns. It may not be possible to remove that inbuilt delay, but there might be a way to configure your hardware to get around it. Could you provide a little more information on what else might be going on in the system?
So appears this is an instrument limitation then when in script trigger generation mode. I'm using the rising edge to the trigger start conversion of a converter then after <300ns I should be able to generate clock signals to access conversion results. Any suggestions on other options to do this? The trigger for conversion should come from other instrument, not from 6556.
To make sure I understand the system, you have a device that generates a trigger. That trigger is sent to both the converter and the 6556.
Once the trigger arrives at the 6556, the 6556 should output a clock signal to the converter. The clock signal should arrive at the converter no later than 300 ns after the trigger -- ideally at the same time.
If this is the case, you might think about using the 6556 to generate the trigger to the converter as well. That way the delay gets propagated on both lines.
If I have misunderstood your application, please correct me.
That’s exactly how the system works. I can’t say the specific reason here but the 6556 is not suitable to provide trigger for the converter, it has to be from an external clock source.
Well, our options were effectively to either introduce delay into the trigger to the converter or to remove the delay from the 6556. As the delay in the 6556 is built into the hardware, and we cannot use the 6556 to introduce an equivalent delay into the trigger, we are out of options.
And if you cannot say what the trigger needs to look like, I'm not sure if I can provide any further help.
If there are no other available modes or methods in the 6556 then it’s a dead end and I’m afraid we can no longer use this module for our apllications. Do you know by a chance if the 6556 firmware can be updated to lessen delay of processing trigger for generation. For a high speed DIO, I think 600ns max delay is too long to process a single bit decision.