PCIe-6536 Simultaneous Read and Write

[acct5]

I have an application where I need to simultaneously read 24 bits (Ports 0-2) and write 8 bits (Port 3), using an external clock.  The way it is done now is I create a read task and I create a write task.  I send my external clock to PFI4 and PFI5, because two clock inputs are required (one for read, one for write).  And I send a trigger signal to PFI3 to start and synchronize the tasks.

However it is not working correctly.  My clock is ~15MHz and the reads and writes are off by a random number of a few clock cycles.  For example when I start writing out Port 3, the reading into Ports 0-2 will start 2 or 3 or 4 clock cycles later.  

Is there a way that I can read and write simultaneously that will work correctly??

[acct5]

I am still trying to figure out this problem.  I want to simultaneously write bytes out of Port_3  and acquire 24 bit words into Ports 0-2.  The only way I know to synchronize the tasks is to have them both start on a rising edge trigger signal on PFI3.

If my clock is a few hundred kilohertz, the tasks are synchonized.  When the clock is over 1 MHz then I start seeing the read of 24-bit words lagging the output write by 1 clock cycle sometimes.  The higher the clock rate, the more delay I see.  With a 20MHz clock I see a lag of 8 or 9 or 10 clock cycles.  I spent a lot of money on this card but it apparently doesn't work as advertised.  It is supposed to work up to 25MHz but I have problems at 1MHz.

The way I am testing it is to loop Port_3 directly into Port_2 with a short ribbon cable (using the CB-2162 test board made for the I/O card).  I can send a pattern out and read it in and see how many of the first bytes were not read in.  For some reason the Acquire task is lagging the Generate task...

[acct5]

I have the older PCIe-6536, maybe it would work if I bought the newer PCIe-6536B, or if I bought a 6537??

[acct5]

I bought a PCIe-6537B and it has exactly the same problem.  At a 1MHz clock or faster, the card cannot write out 8 bits and read in 24 bits simultaneously without them being out of sync.  This DIO card does not work as advertised.

Is there an NI Applications Engineer on the forum that can recommend a way to read and write data simultaneously without the reads and writes being off by a random number of clock cycles?

Any help would be appreciated.

[HeisenBerger15]

Hi acct5.

I'm sorry no one responded to your question before you purchased a new card. 

In order to fully troubleshoot this with you, please attach the most simple version of the VI that you see this behavior in.

-CB

[acct5]

Thank you for offering to help!

I am programming in C++, not LabView.  Here is the code that is setting up the read/write.  In this example I am writing from Port3 directly into Port2, in order to test simultaneous write/read.

//Create tasks
	DAQmxErrChk(DAQmxCreateTask("Receive", &Port2_taskHandle)); // Create task for receiving data
	DAQmxErrChk(DAQmxCreateTask("Generate", &Port3_taskHandle)); // Create task for generating data;
	DAQmxErrChk(DAQmxCreateTask("Trigger", &PFI2_taskHandle)); // Create task for triggering. PFI2 is connected to PFI3 i.e. PFI2==PFI3;

	//Create DO and DI channels
	DAQmxErrChk(DAQmxCreateDIChan(Port2_taskHandle, "/Dev1/Port2", "Port2", DAQmx_Val_ChanForAllLines)); // setup digital input
	DAQmxErrChk(DAQmxCreateDOChan(Port3_taskHandle, "/Dev1/Port3", "Port3", DAQmx_Val_ChanForAllLines)); // setup digital output
	DAQmxErrChk(DAQmxCreateDOChan(PFI2_taskHandle, "/Dev1/PFI2", "PFI2", DAQmx_Val_ChanForAllLines)); // setup digital output

	DAQmxErrChk(DAQmxCfgSampClkTiming(Port2_taskHandle, "/Dev1/PFI5", 1000000.0, DAQmx_Val_Falling, DAQmx_Val_FiniteSamps, SAMPLES)); //setup clock
	DAQmxErrChk(DAQmxCfgSampClkTiming(Port3_taskHandle, "/Dev1/PFI4", 1000000.0, DAQmx_Val_Rising, DAQmx_Val_FiniteSamps, SAMPLES)); // setup clock

	DAQmxErrChk(DAQmxCfgDigEdgeStartTrig(Port2_taskHandle, "/Dev1/PFI3", DAQmx_Val_Rising));	//Configure trigger signal
	DAQmxErrChk(DAQmxCfgDigEdgeStartTrig(Port3_taskHandle, "/Dev1/PFI3", DAQmx_Val_Rising));	//Configure trigger signal

	
	DAQmxErrChk(DAQmxRegisterEveryNSamplesEvent(Port2_taskHandle, DAQmx_Val_Acquired_Into_Buffer, SAMPLES, 0, EveryNCallback, NULL));

[acct5]

Always a random number of clock cycles of delay between the read and write.

[nslager]

Hi all,

Has anyone resolved this? I'm about to create a read/write application.

@acct5 I'm assuming you're using an appropriate NI cable. I know you're using DAQmxRegisterEveryNSamplesEvent(), but I wonder if the "Number Of Warmup Iterations" property applies here too? (The documentation mentions this property when using DAQmxWaitForNextSampleClock() + a NI-DAQmx Read function). It says there's considerable jitter for the first ~100 "iterations".

Nate

[Kevin_Price]

Will your app also be on for a 6536 or other board from the same family?

I don't have direct experience with those particular boards, but I would expect a loopback test to be more consistent and reliable than what was reported.  But it would need to be configured and run properly, and there isn't enough info in the prior thread to assure this.

I'm suspicious of the line:

	DAQmxErrChk(DAQmxCreateDOChan(PFI2_taskHandle, "/Dev1/PFI2", "PFI2", DAQmx_Val_ChanForAllLines)); // setup digital output

In my experience with many other NI devices, it isn't normal to identify a digital output *channel* using PFI notation.  I'd expect to need Port and Line notation for channel identification.

There are other possible gotchas related to when tasks are started, when trigger signals are asserted, how the read and write data is managed and correlated, etc.

It also may be the case that the O.P. had everything exactly right and there's a real underlying issue.  The "random" timing offset is down in the microsec realm, smaller than I'd expect from the gotchas I mentioned above.

For troubleshooting, I'd try to use direct read/write methods rather than relying on the relatively opaque DAQmx Events.  If you run into similar troubles, post (all) your code.

-Kevin P

[nslager]

Yes, NI PCIe-6536. However, it seems I'm unable to use the DAQmx_Val_HWTimedSinglePoint timing mode (see stripped code at bottom):

>main.exe
DAQmx Error: Requested value is not a supported value for this property. The pro
perty value may be invalid because it conflicts with another property.
Property: DAQmx_SampQuant_SampMode
Requested Value: DAQmx_Val_HWTimedSinglePoint
You Can Select: DAQmx_Val_FiniteSamps, DAQmx_Val_ContSamps

Task Name: write_task

Status Code: -200077

Is DAQmx_Val_HWTimedSinglePoint not supported on the NI PCIe-6536? The documentation online seems to neglect any mention of 65XX devices.

I also get an error if I move the DAQmxGetDODataXferMech() before DAQmxCfgSampClkTiming():

>main.exe
DAQmx Error: Specified property is not supported by the device or is not applica
ble to the task.
Property: DAQmx_DI_DataXferMech
Channel Name: write_channel

Task Name: write_task

Status Code: -200452

It's not critical that my input synchronize with my output (for now) --I just need to know random number of clock cycles of delay between the read and write (can be solved offline by sending a known pattern in a loop back fashion first, I guess). So I'm thinking I'll try the DAQmxRegisterEveryNSamplesEvent() route next.

// Control National Instruments PCIe-6536 interface:

#include <stdio.h> /* printf(),  more */
#include <stdlib.h> /* snprintf */
#include "include/NIDAQmx.h" /* LabView hw calls */
#include <Windows.h>
#include <windows.h>
#include <conio.h> /* kbhit() */

#define SAMPLE_CLK_FREQ (1*400*1000) 
#define DAQmxErrChk(func) if(DAQmxFailed(res=(func))) goto Error; else

int main() {

    TaskHandle write_task=0;
    int32 res=0;
    char errBuff[2048]={'\0'};

    DAQmxErrChk(DAQmxCreateTask("write_task", &write_task));
    DAQmxErrChk(DAQmxCreateDOChan(write_task, "Dev1/port0/line0, Dev1/port2/line4, Dev1/port0/line2, Dev1/port0/line4, Dev1/port0/line6, Dev1/port1/line0, Dev1/port1/line2, Dev1/port1/line4", "write_channel", DAQmx_Val_ChanForAllLines));

    DAQmxErrChk(DAQmxCfgOutputBuffer(write_task, 0));
    printf("DAQmxCfgOutputBuffer: %d\n", res);

    DAQmxErrChk(DAQmxCfgSampClkTiming(write_task, "/Dev1/PFI4", SAMPLE_CLK_FREQ, DAQmx_Val_Rising, DAQmx_Val_HWTimedSinglePoint, 0));
    printf("configure write sample clock timing (PFI4, from FPGA): %d\n", res);

    int32 dataxfermechanism;
    DAQmxErrChk(DAQmxGetDODataXferMech(write_task, "write_channel", &dataxfermechanism));
    printf("data transfer mechanism: %d, res: %d\n", dataxfermechanism, res);
    
    return 0;

Error:
       if( DAQmxFailed(res) )
              DAQmxGetExtendedErrorInfo(errBuff,2048);
       if( write_task!=0 ) 
              DAQmxStopTask(write_task);
              DAQmxClearTask(write_task);
       if( DAQmxFailed(res) )
              printf("DAQmx Error: %s\n",errBuff);
              return 0;
}