PCIe-6535B DO timing sync

[WayneS3]

Looking through the datasheet, it isn't clear to me the tolerance of individual digital output bits that I want triggered at the same time. I inherited a piece of hardware with a latching circuit that used one DO as a clock to ensure all signals were sent simultaneously. I'm guessing that it isn't necessary with this DIO card, and was just legacy from before. 

Can someone point me to which section of the datasheet pertains to my particular condition? 

Additionally, I'm still trying to understand the specification requirements on what can be tolerated from the setup. 

[JKSH]

I'd like to find out more about DO synchronicity too.

Someone I know who had a PCI-6512 tried to toggle multiple channels simultaneously (e.g. by writing an array into DAQmx Write). He found that:

• There is a lag of up to 60 ns between 2 lines on the same port
• There is a lag of up to 11 µs between 2 lines on different ports

Has NI done any benchmarking on DO timings? Does the PCIe-6535B have "better" internal syncrhonization compared to the PCI-6512? How do I find out the maximum timing discrepency between any 2 channels on a single DO module?