Hi Olivier,
it's me again...i've made some progresses since the last time we talked, i have change my PWM generation and i think i now have my FPGA and my HOST synchronised cause i'm not getting the overflow condition as much as i get before. At the acquisition i still have some doubts, in the waveform graph seems that my periods take a half of a desired period more in each period i that i generate, but in the scope the period generation is fine. Can you give me an idea to fix this??
Thanks
Regards
Mário
