If I use an external clock on my NI 6561 card arriving on CLK IN pin, as a square wave with a rising/falling edge of around 8 ns, and
I export the sample clock to DDC CLK OUT pin, will the transition time of my exported clock (LVDS) be 1 ns as specified in NI specs document?
Thanks for posting to the NI Discussion Forums.
Yes it is, DDC CLK OUT have 1ns maximum rise/falling edge, this time is take between 20% and 80% transition.
I have question about your system, why do you want route clock in to clock out?
National Instruments France
I need a 36 MHz clock, so I need an external clock imported to CLK IN, and I also need to export the 36 MHz LVDS clock to the DUT, so I export it to DDC CLK OUT.
Thanks for your reply,
I just wanted to mention that you can also consider using the Data Delay feature of your HSDIO board in order to make sure that you sample the data properly on your DUT. You can use Sample Clock Rising Edge, Sample Clock Falling Edge, or Delay from Sample Clock Rising Edge to adjust your data position. Just another option to think about when generating your data.