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Multiple Independent Pulse Trains with cDAQ-9172

Hi All,

 

I want to have a 2D array where each line in the array corresponds to a state of the DO lines on an 9472 module.  I want to switch from one state (line in the array) to the next with a characteristic time "dt", which will range between 10msec and 200msec.  This is part of a much larger VI where I want the user to be able to change both the pattern AND the dt at run time.  The cycling between states need to be managed with hardware becuase I will also be doing video rate imaging at the same time.

 

What I am posting here works for ONE pattern (as long as the DO module is in slot 1-4), but I need this to work for 2 different patterns, that can have different patterns, numbers of states, and characteristic times.  I had initially hoped to do this one one module, but that is an obvious no.

 

The top branch of my VI works exactly how I want it to.  The bottom branch does not.  I get an error code (reproduced below) that makes me realize that perhaps with the 9172 this approach will not work. 

 

I though because there are 2 counters _ctr0 and _ctr1, that this would work, but I think the error is telling me they both need access to a common resource, the "SampleClock".

 

So, can someone translate the error for me, or even better, guide me towards a workable solution.  I know there is an example in about this using the 9178, but that is not in my budget anytime soon.

 

 

Begin Error Code

====================

Error -89137 occurred at DAQmx Write (Digital 1D U8 1Chan NSamp).vi:4

Possible reason(s):

Specified route cannot be satisfied, because it requires resources that are currently in use by another route.

Property: SampClk.Src
Property: SampClk.ActiveEdge
Source Device: cDAQ1
Source Terminal: Ctr1InternalOutput

Required Resources in Use by
Task Name: _unnamedTask<EA>
Source Device: cDAQ1
Source Terminal: Ctr0InternalOutput
Destination Device: cDAQ1
Destination Terminal: do/SampleClock

Task Name: _unnamedTask<E9>

==============================

End Error Code

 

Hardware Available: cDAQ-9172, NI-9472 x2

LV Versions: Prefer a 2009 solution, but can take any version.

 

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Hi Munson1027-

 

     The issue here is that you only have one digital output timing engine on the 9172; therefore, you can only have one digital output task.  The 9174/8 also only have one digital output timing engine, wo you would be in the same boat with this code.

 

     You will need to either use a digital output task with an array of data sent in to the DAQmx Write.vi (the different dimensions in the array correspond to the different channels on your device) or you will need to use two separate cDAQ chassis or a PCI card along with your cDAQ chassis.

 

     I hope this helps.  Thanks and have a great day!

Gary P.
Applications Engineer
National Instruments
Visit ni.com/gettingstarted for step-by-step help in setting up your system.
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Thanks Gary.

 

This is a bit disappointing.  Seems like this question comes up on the boards every few months. 

 

Is there some reason that NI does not build multiple DO timing engines into the cDAQ modules?  There are three AI timing engines, why not 3 DO engines?  I am sure there is a reason, but I am not an electrical engineer, so I don't have the first clue what that reason is.  Someone educate me (just a little though).

 

Is there some way I can submit as a user, that having that capability would be of ENORMOUS benefit to me in some future device?  Is there some other NI platform (other than cDAQ) that can allow me to do this?  Again, software timing is NOT an option, unless I get a second PC.  Although come to think of it, it seems ridiculous, but a second PC might be the more cost effective solution (crazy!).

 

Thanks

Matt

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Adding three AI timing engines is a relatively new concept introduced to CompactDAQ with the cDAQ-9174 and cDAQ-9178.  The reason for adding three AI timing engines instead of 3 digital timing engines is that AI modules have the widest variation in possible sampling rates.  

 

Adding additional timing engines requires additional circuitry and cost.  The majority of the time performing digital operations at different rates on different lines can often be handled in software either choosing an input or output rate that can be evenly divided into the desired digital rates or by using the onboard counters.  While the calculation of the mutually acceptible rate can get complex, it is almost always possible.

 

If your needed pulse train update rates that can't be lined up with a faster rate, you may want to look into using CompactRIO and doing the programming on an FPGA.  FPGA provides nearly infinite flexibility with regards to timing digital signals at the tradeoff of being harder to program and deploy. 

Seth B.
Principal Test Engineer | National Instruments
Certified LabVIEW Architect
Certified TestStand Architect

Engineers like to solve problems. If there are no problems handily available, they will create their own.
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@Seth B. wrote:

 

Adding additional timing engines requires additional circuitry and cost.  The majority of the time performing digital operations at different rates on different lines can often be handled in software either choosing an input or output rate that can be evenly divided into the desired digital rates or by using the onboard counters.  While the calculation of the mutually acceptible rate can get complex, it is almost always possible.


Can you point me to some examples of this?  It sounds like just the thing for me!

Thanks

Matt

 

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This is an extremely basic example of what something link this might look like.  If you know what rates your user can choose more precisely, you might be able to come up with more intellgenet rates.  For instance, for your example of 250 and 333 Hz, if 333.333... Hz is acceptible, your update rate could be 1000 Hz and you'd output 4 duplicates of the array for the first array and 3 duplicates of the second array at 1kHz and repeat that pattern for as long as you want it to run.

 

 

Seth B.
Principal Test Engineer | National Instruments
Certified LabVIEW Architect
Certified TestStand Architect

Engineers like to solve problems. If there are no problems handily available, they will create their own.
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