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Miss sample HSDIO 6552

Hi,

 

I m seeking the proper way to generate and acquire back the signal, by NI flying lead cable, as same as scenario described in

 

http://digital.ni.com/public.nsf/allkb/A70921E707DF94C0862571D800097A7C

 

I am now set the generation clock (falling edge) and acquisition clock(rising edge).

The clock exported to be strobe back.

PFI1(Date active event) to PFI2(Start Trigger).

 

*Same length for all connector or jumper

 

And when I strobe back the signal, Let say DIO0 connected to DIO1, 

L 0

H 1

L 0

H 1

L 0

H 1

L 0

H 1

.. until (100 lines)

 

For 10-20MHz, it run smoothly. But when I adjust the frequency to 40MHz/66.67MHz/100MHz, errors will occurs. Sample miss or Sample been shifted. 

 

So, I m here to ask for suggestion and solution about the problem describe above. Thousand thanks in advance. 

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Hi engwei,

 

When you say you set your generation clock to falling edge, what do you mean?  Did you set up the exported clock to be inverted, or did you set your data to position to Falling Edge?  What position (rising or falling) is your data active event?  Is your start trigger set to rising edge?

 

Can you post your VI?

 

Thanks!

 

Keith Shapiro

National Instruments R&D

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Hi Keith, 

 

Thanks for your reply. 

 

When you say you set your generation clock to falling edge, what do you mean? 

Generate the signal on the rising edge of clock and acquire on the falling edge of clock

 

Did you set up the exported clock to be inverted,

No

 

or did you set your data to position to Falling Edge? 

Generation (falling edge) of the clock , acquisition (rising edge) of the clock

 

 

What position (rising or falling) is your data active event?  Is your start trigger set to rising edge?

Since generation clock (falling clock), so data active event I have set it to falling edge. 

Since acquisition clock been set to rising edge of clock, so start trigger I set it to rising edge.

 

The VI is almost same as posted in http://forums.ni.com/ni/attachments/ni/70/9458/1/Hardware%20Compare%20-%20Error%20Locations.vi

but the setting has been changed to current setting (as described in this post).

 

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Hi,

 

Now I set all generation and acquisition clock, trigger to rising edge. Data active event (active high). 

And the result is OK. Showing the expected result. But ..

 

When I run the pattern in 66.67MHz, the pattern will properly displayed on the graph. (Strobe channel, i.e. Ch6 in this case)

But, if I run the pattern in 100MHz, some pattern will missed. 

 

Ch5(Generate) connected to Ch6(Acquisite).

 

Hardware comparison result for both 66.67MHz and 100MHz is same, and as expected. 

Here I attached the screenshot. Is that possible to get proper acquisition data to display on the graph?

 

Please take a look. Thanks. 

 

 

 

Message Edited by engwei on 12-29-2008 12:34 AM
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Message 4 of 8
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Hi engwei,

 

It seems to me that you're confusing the polarity of a signal (active high vs. active low) with data position (when the data occurs).  For example - setting a rising edge start trigger looks for a rising edge (active high polarity) of the input trigger.  However, the start trigger will sample at the rising edge of the clock (data position) unless you explicitly set the position of that trigger through a property node.

 

Similarly with exported events.  Even if you configure the data position of your data channels to be falling edge, exported events (like data active) must be set up separately through a property node.

 

The situation you've described seems to me like a timing problem, if the runs alternate between missing or shifting samples.  Please try setting the data position on your data active event to match that of your data.

 

--

 

With your second setup, the VI you posted uses On Board Clock as a clock source for both acquisition and generation.  Since you're using a loopback cable, it really makes more sense to use source synchronous clocking (exporting your generation clock to DDC Clock Out and receiving the clock back in on Strobe).

 

To be honest, I'm confused by what you're trying to do.  The image you attached looks like you're acquiring JTAG data.  What's your clock source?  What does your system look like?

 

Keith Shapiro

National Instruments R&D

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Hi Keith, 

 

Thanks for your reply. The missing or shifting of samples has been solved. 

Ya, I m using Onboard Clock as clock sources. 

And about "exporting your generation clock to DDC Clock Out and receiving the clock back in on Strobe", I have connected the cable in this way all the time.

 

Sorry for not futher explaining the waveform.

Ch0 - Ch4  (Generation Channel)

Ch5            (Acquisition Channel)

Ch6            (Generation Channel - mistakely state as acquisition channel on last post)

(It is somesort like JTAG test)

 

For this case, Ch0-Ch4 is opened. 

Ch5 connected to Ch6 (loopback).

 

Here I paste a part of the pattern

Ch5 Ch6

X     X
X     X
L     0
H     1
H     1
L     0
H     1
L     0
L     0
L     0
L     0
L     0
L     0
L     0
H     1
L     0
L     0
L     0
L     0
H     1
L     0
L     0
L     0
L     0

 

From the graph, data of Ch6 does not displayed (or properly acquired at Clock speed of 100MHz). 

It is expected that Ch6 will acquired it own generated data, as display on graph labeled 66.67Mhz.

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Hi engwei -

 

You said that missing samples was solved.  Are you still having trouble?

 

Thanks!

 

Keith Shapiro

National Instruments R&D

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Hi,

 

Ya, the pattern is properly generated and acquired with no missing since hardware compare showing no error (indicate the proper data is acquired).

 

But, there is another missing there..

Although the data is properly compared by hardware compare (no error ), but it doesn't properly acquired and displayed on the graph.

Refer to the 100MHz graph and 66.67MHz graph, and u will get what I mean.

 

Thanks.  

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