I don't get CLK out with PCI 6561

[EHE]

Hello

I am running TestPanel application of DAQ PCI6561 and try to monitor the CLK out pin by scope (50ohm DC coupling)  , but i don't see any signal out.

please help me to understand what are the requirements for clk signal receive?

[David S.]

Hi Herman -

You have to explicitly tell the device to export its clock to the CLKOUT pin.  The test panels in MAX don't provide this option, so you'll have to use a program in your preferred language to achieve this. There are several example programs provided with the NI-HSDIO driver.  If you're using LV, you can run this one to export the clock: Dynamic Generation with Exported Clocks.vi

You'll also have to consider which pin you're trying to probe.  The 6561 is a differential device, and its clock is exported to either LVDS or LVPECL outputs.  If you're probing the LVDS pins (66/65), you'll need to provide a 100-Ohm termination instead of 50 Ohms. (See http://www.national.com/appinfo/lvds/files/lvds_ch1.pdf) If you're probing the LVPECL pins, you'll need to consider proper termination for that standard, too.

[JuanCarlos]

In addition to creating a program to export the clock you can use Signal Express to have a more advanced test panel that will allow you to export the clock. Signal Express is shiped free with the lattest driver, just open SigX, drop and configure an HSDIO block and hit play. Just my 2 cents. Juan Carlos

[David S.]

Touché, sir.