Have Dedicated Clock Line while Being Able to Use Rest of Lines on HSDIO Card

[Nycor]

I need to dedicate one of the lines on the PCI-6542 as a clock to my DUT. While the clock line is clocking the DUT I would like to be able to dynamically or statically control the other 31 lines on the PCI-6542 and not having to rely on a while loop in order for the clock to be at the DUT all the time.

Has anybody been able to implement a clock output while being able to acquire or generate other signals on the HSDIO card?

[dbell0971]

Hi Nycor,

Most commonly, users export the sample clock of the 6542 to the DDC Clock Out line of the 6542 (pin 33).  You can use the "HSDIO- Export Signal" VI to export the sample clock to the DDC Clock Out, then LabVIEW will route the sample clock to the DDC Clock Out when the task is started (you don't need to write anything to pin 33 in the while loop).

Are you using LabVIEW to control your 6542?  We have several examples that install with the HSDIO driver, I'd recommend looking through those, particularly "Dynamic Generation and Acquisition - Source Synchronous" if you get a chance.

Thanks,

David B

National Instruments

Applications Engineer

[Nycor]

David,

Yes I am using LabVIEW. Unfortunately the various type of DUTs that I need to support have up to 4 different lines per DUT that require static high/low input signals in addition to the clock input signal on the same inputs. Also these inputs are not always on the same pins so I need to utilize other lines for those.

I was hoping that the PCI-6542 HSDIO card would allow each line to be a clock either using DMA or some other method to have that line clock away to the DUT without utilizing all card resources and having to put the niHSDIO Is Done.VI in a While Loop just to generate a continuous signal.

[dbell0971]

Hi Nycor,

I'm not quite sure what you mean by, "static high/low input signals in addition to the clock input signal on the same inputs".  Can I ask how static signals and the clock are supposed to be on the same line?  Also, it sounds like you want to be able to generate clock signals on each data line without having to run a VI or a task, does that sound right?

As to what the 6542 can do, the 6542 can route the sample clock with relative ease (1 VI) out to the DDC Clock out line and the Clk Out line.  If you are trying to supply a clock to your DUT, I would recommend routing your sample clock out to the DDC Clock Out line so that your I/O is synchronized with your clock.  You can also use one of the data lines to generate a clock as well and use the rest of the data lines for your task.

Thanks,

David B

National Instruments

Applications Engineer