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Hardware compare with pxi-6552

Im using PXI-6552 and i like to to peform a BERT test (scan test). To perform the test, the stimulus data (8 signals loaded on the on-board memory), is generated and the expected data (3 signals) is stored in the FIFO.  The deserializer accepts the serial stimulus data and outputs the expected data.  The parallel data is then read in on the input pins on the PXI-6552 and compared with the expected data stored on the FIFO. Im using the example  "Hardware Compare - Error Locations.vi". To test and see that its working i generate 3 "drive" signals in NI Digital Waveform Editor and then i convert it to "compare" signals. On the generation side the sample clock is exported to the ClkOut pin on the Digital Data and Control Connector (DDC) by connecting the ClkOut pin on the Digital Data and Control Connector (DDC) to the Strobe line. A trigger is shared between the generation and acquisition sessions for complete synchronization.  An external connection also needs to be made between the lines PFI1 and PFI2 on the DDC. The poblem is that i have errors although im using the same signals on both generation and acquisition part(im using same length on cables).  And if im changing the clk rate to a higher rate then i get less errors but i still get errors. So my question is what am i doing wrong?

I attach the HWS file (replace file ending .txt with .hws) and the labview example im using.

 

 

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Hey Maximus1977,

 

It sounds as if you are taking the right steps in your system, although the one part that might be throwing off your data that I could see would be the deserializer. So one thing that I would recommend you try out is to test your system without any deserializer (or serializer) involved. Test out the code with the way the Example does it, which says to hook up certain channels to other channels. So in your case, you could use ch. 0-2 for generation, and 3-5 for acquisition. Because the clock and trigger travel the same distance the timing when the acquisition occurs is in line with the clock. If you insert a deserializer into the equation, then the clock is no longer in synch with the data. There might be a few clock cycles that it took the data to go through the deserializer, so you would have to compensate for that on the acquisition side, either using data delay, or by adding a certain number of X's to the beginning of your Compare data to compensate for the number of samples that the deserializer delays the data.

 

I hope this helps. Please let me know whether or not your test without a deserializer works, and if adding in extra samples corrects the number of bit errors that you get. Let me know if you have any other questions or concerns. Thanks, and have a great day.

 

Regards,

DJ L.

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