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HSDIO 6555 hardware comparison with acquisition delay


I am developping a Labwindows /CVI automatic test

My goal is to simulate a burst of digital signal ( around 100KHz) and acquire it behind my DUT. I have to check that the signal is received within 1.5µs.

I want to generate the stimulus from a file and do the hardware comparison with a response file as per the example code :ErrorRateTest

For now I use the same niHSDIO PXIe6555 board to generate and acquire. My hardware setup do not let me use clock and event export on the connector


So that, I use a free DIO to generate a "flag" which trigger the acquisition as the acquisition is configured with "niHSDIO_ConfigurePatternMatchStartTrigger(vi,...)" function. As soon as the acqusition see a rising edge on that specific channel, it starts the acqusition.

My channels dedicated to generation pattern are triggered on onboard clock rising edge

My channel dedicated to lunch the acquisitions is triggered on onboard clock rising edge

My channels dedicated to acquisition are triggered on onboard clock rising edge + acquisition delay

It works. I can check how many sample error and read back the reply using niHSDIO_FetchWaveformU32 to visually compare it with my expected pattern.


But as soon as I add acquisition delay, very small (0.01), it seems that I miss the first sample.

I think the delay must be a section of the sampling period. For my neeed, 1.5µs is about 0.15 to 0.45 depending my sample frequency (100 - 300 KHz).

Am I doing wrong with the delay? or is there something I have to take into account?





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