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FPGA SPI share clock

Hi,

 

I would like to create an Interface which can write SPI (Digital IO) but read different format (Analogue port), there is a problem as I need to use the same clock.

 

I have been looking at "http://www.ni.com/white-paper/9117/en/" but this is only a SPI I need to maintain SCLK (Digital IO) in order to read from the Analogue port (Synchronize) X number of sample.

 

I am not sure if I should have one SCLK vi (starting by global definition) or have two interface assessing the same SCLK IO?  

 

The Hardware: is a NI5751 terminal.

 

Thanks

 

 

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Message 1 of 10
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Hello, 

 

Would it be possible for you to attach your code to a post here so i can see exactly what it is you are doing/ trying to do?

Kind Regards

CameronW
National Instruments
Applications Engineering
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Hi!

 

 

I don’t have a code to give you yet because I am learning from the SPI example. I am considering the route to take, at the moment thinking, I could modify the code example to support SPI to write and different interface to read as I need to maintain SCLK clock to read.

 

There is another possible solution I see that is create a global definition SCLK and have SPI vi changing the state of the global definition and have one vi only driving the SCLK clock and another vi reading analogue channel and changing state that global definition. Is there a better Idea? Would I have problem in details with the global definition?

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Hello,

 

Just a couple of questions to make sure i give the correct advice.

 

Are you using an FPGA for both the read and the write operations? How fast do you need these to go? What is it you are hoping to do using them?

 

 

 

 

 

Kind Regards

CameronW
National Instruments
Applications Engineering
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Yes I am using the FPGA card to perform write and read (not at the same time). The fastest I would like it to go is 10 MHz on reading but I could write slower rate. I am planning to write (configure a device) then read from analogue in order to perform a test.

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Hey,

 

Im sorry but you've confused me slightly. If you are reading at 10MHz and can write at a slower rate then why is it you need the same clock? What is it exactly you are trying to do, do you just want to perform a write and read and send that data elsewhere to perform a test?

Kind Regards

CameronW
National Instruments
Applications Engineering
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Message 6 of 10
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Hi!

 

Because one of the requirements is that to read I must provide a source clock (in this case SCLK) I need to maintain source clock otherwise It will not work. I want to write (configure device) the maintain clock SCLK and read synchronously to that clock. After that I will perform test in the same machine (After grapping a finite amount of read out) but now I just need to get the data from the FPGA vi. Hope this help!

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Message 7 of 10
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Hey,

 

I am still a little confused why you need to maintain the clock between the read and write and if you are writing to configure the device surely that would be a one time process, unless you are planning to reconfigure it multiple times during execution. Is it that the read requires a source clock input? would it be possible for you to attach the example code you are using? Sorry if i am missing something blatantly obvious by the way. 

Kind Regards

CameronW
National Instruments
Applications Engineering
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Message 8 of 10
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Hey,

 

Is it just that you want to include timing in your read and writes? In which case the best way to do that would probably be to put timed loops around them and set the timed loops to run off a 10MHz clock that has been derived from the FPGA 40MHz onboard clock, 

Kind Regards

CameronW
National Instruments
Applications Engineering
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Message 9 of 10
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Now we are talking about time loop the original SPI example have a time loop in the main SPI vi but it does not work I get compilation errors. I research on-line and I found a suggesting changing the time loop by a while loop. I think it’s a problem between FIFO reading/writing and time loops.

Yes I need to maintain clock source or I will get nothing to read. Yes the idea is I could configure device then read X number of sample and the reconfigure and read again or read continually after configuration.

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