05-07-2020 08:59 AM
Hello,
We have a PXI system in my organization (PXIe-1062Q and PXIe-8840) that we are looking into upgrading with a PXIe FlexRIO and a 658x modules.
The idea is to control several Integrated Circuits (ICs) from the PXI, among others, high speed ADCs, such as AD9649 or AD9245.
The AD9245 needs a CLK single-ended input signal, of up to 80 MHz with low jitter (in the order of units of ps rms). Is it possible to generate this kind of signals with a PXIe FlexRIO module?
On the other hand, a device such as the AD9649, provides a single ended data clock output signal (DCO), to synchronise data acquisition. I have seen approaches where this signal is configured as a digital input to the FPGA (like in this post), which is sampled to look for edges. I was wondering, would it be possible to import this DCO signal as a clock signal within the FPGA (as explained here) and then use this clock as a SCTL clock? What would be the specifications of this signal (in terms of duty cycle, jitter, etc.) from the FlexROP/658x module point of view?
Best regards,
Isacar.
06-22-2020 07:57 AM
Hello
lsacar
I recommend you to check this document
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000P6OeSAK&l=en-US
If you still have this problem I suggest you to open a service request
Have a nice day