Digital Output Delay cRIO 9474

[DavCas]

I'm working with a compactRIO 9002, chassis 9102 and C-series module NI-9474 with 8 digital
outputs.

I try to generate a square signal but when frecuency is less than 50 or 60 Hz, the signal become to distor
and it can change from +V to 0.

Data sheets says that "Output delay time" = 1 us, so it seems posible to work with signals of several
kHz.
I'm worry about the way to program compactRIO.

I attach the fpga VI and the compactRIO VI, they are two very simple codes.

Thanks for all.

[Castel]

Hi DavCas,

you can view information about how to create a square wave on thid web document:

http://zone.ni.com/devzone/cda/tut/p/id/3254

On attached you can see an example that shows you how you could program the FPGA to achieve the frequences you need.

I've created this very simple example with Labview 8, so if you is using a previous version you can see the FPGA code on the attached image.

Regards

MarcoC

[DavCas]

Thank you very much!!!

it was simple and very useful.

[radim.stefan@ni.com]

The "High time" and "Low Time" labels in the code and JPG above is the other way round...