Digital Filter for Digital IO

[bmann2000]

This may sound strange, digital filters are traditionally used to filter analog signals, but I need a filter for a digital signal.

I'm using a cRIO-9401 module to sample digital inputs, but due to system noise, sometimes I register a logic low when the input if actually at 5V, a look on the scope has revealed that occasional noise spikes below the TTL threshold are causing logic-0 levels to be briefly registered on the cRIO.  The sampling rate of the digital input is 30Mhz, therefore, even though the noise spike only lasts for a tiny amount of time, the cRIO picks this up as logic-0. 

I figure I need to implement a digital filter, preferably in a way that can be tuned to strike a balance between missing logic-0's and not recording noise spikes as logic-0.  A real event would last for at least 10mS.  Has anyone encountered this problem before, and has code?  I can think of a few ways to implement the filter, but wondered if anyone had tried and tested code.

Thanks in advance for your suggestions.

[JB]

An easy solution is to read the DI several times (with a given time interval) and then make a logical AND by an Add Array Elements function.



This may not be a solution for you if the read has to be really as fast as you mentionned.


Message Edité par JB le 03-27-2008 04:05 PM

[PhillipBrooks]

I don't work with CRIO, but some of the NI DIO devices that include and FPGA support digital debounce. I searched the NI web site and found this page that might be of help:

Advanced Data Acquisition Techniques with Intelligent DAQ

[bmann2000]

thanks JB & Phil, link to debounce code looks best, tunable, small amount of code, cRIO specific, thanks very much.

here it is again: