From 04:00 PM CDT – 08:00 PM CDT (09:00 PM UTC – 01:00 AM UTC) Tuesday, April 16, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
What is output on DDC CLK OUT is dependent on what signal you tell to be exported to this output pin based on the niHSDIO Export Signal VI. I have included the help page here below. The signal input is what you will be exporting to DDC CLK OUT, and you can see the list of available signals at the bottom of the help page. Can you explain a little more about your application, or what you are exactly trying to do?
Yes, using the niHSDIO Export Signal VI will allow you to export a clock to this pin. The sample clock will only export while you are actually sampling, so if you do a finite task you will be able to export for N-cycles. Have you been able to test this to see if this does what you want?
Yes, using the niHSDIO Export Signal VI will allow you to export a clock to this pin. The sample clock will only export while you are actually sampling, so if you do a finite task you will be able to export for N-cycles. Have you been able to test this to see if this does what you want?
-will.i.am10
As I can understand from datasheet, on ddc clk out is only continious. So if generate in finite mode, the max frequency on dio can be 100 MHz. How can I reach 200 MHz?
Have you tried to export a signal onto the DDC CLK OUT pin? As mentioned earlier, you should be able to export the signal you are after onto the pin using the process linked above. What issues have you run into while exporting a signal onto the DDC CLK OUT pin?
