Controlling PI Piezostages via"non-standard" SPI on PCIe-7842R FPGA

[JCard]

I am trying to control two ultra fast piezo stages from PI via their SPI interface. However, for their protocols, their SPI interface has 6 datalines, with four of them being the "standard" SCLK, MISO, MOSI, and CS, and two extra lines being LDAT and DCLK. PI has their GCS command structure that I have used to program other non FPGA target in LabVIEW, however I'm not sure how to modify the "standard" SPI structure used in the example VI's I've found to accommodate. Any insight would be much appreciated! I've attached my basic VI I've used to start based off of example programs I've seen. 

[cweeks12]

I tried to see what those other lines do, but I personally couldn't find any documentation on it. Essentially, all you'd do is program the logic into the program that those other pins do and put those into the logic. For example, it looks like DCLK, may potentally be the differential clock, so just "not" the clock signal and put it out. It just depends on what those lines are required to do.