Can I use PCI-7811R to acquire 20MHz serial A/D data?

[UFox]

Hi, I have a A/D board which ouput data through a serial interface, the signal timing and format are shown in flowing figure:

 

CLK is 20MHz data clock, FS is frame start signal (falling edge indicates start of new frame), 

each frame contains 8 x 16 bits data for 16 channel A/D.

Is 20MHz CLK too high for 40MHz 7811R FPGA to sample the DAT signal?

[huyu]

我认为可以，你可以考虑使用单tick循环来提高运行精度