Acquisition Error with HSDIO 6552

[engwei]

Hi,

I have a program to gen. and acq. signal dynamically, and I have found an error acquisition when I m trying to generate

1 0 1 0 1 0 1 0 1 0 

the acquired signal would be

1 0 1 1 1 0 1 0 1 1

for example.

I have refer to the link http://digital.ni.com/public.nsf/allkb/DA079008D7085E958625737D0078BB04 and I understand that this is mostly due to the error described in title "Driving a line while acquiring"

Is it any idea to enable tristate ON and OFF function while doing dynamic gen. and acq. ? My case is very similar to

LabVIEW 8.6\examples\instr\niHSDIO\Synchronization.llb\Multi-Device Dynamic Generation and Acquisition-Source Synchronous (TClk).vi

(with waveform script function)

Any comments are welcomed. Thanks in advance. 

[Ryan_M]

Are you acquiring on the same channel from which you're generating?  If this is the case then keep in mind transmission effects.  The receiver is at the source in the case.  You'll end up with the stair step effect at the receiver which will be at a 50% level which could read one way or the other depending on your thresholds.

what device are you using?  The 655x has hardware timed tristates by using a Z value in your data waveform.

Message Edited by Ryan M on 09-17-2009 08:40 AM

[Keith.Shapiro]

Additionally, it is possible on the 6552 to tristate your channels as you write your output waveform.  The feature is called Cycle To Cycle Tristate.  There is an example program in the HSDIO Dynamic Generation (Dynamic Generation with Cycle To Cycle Tristate.vi) example library.

If you search for "tristate" as a keyword in the LabVIEW example finder, it should pop right up.

[engwei]

Hi,

Thanks for you guys' reply.

I m actually running all 20 channels in bidirectional, means pattern like

1 0 1 0 Z Z H L Z Z 0 1 

is possible. Anyway, usually the pattern will be inserted at least 2 cycles of tristate to avoid the problem discussed by Ryan here.

The 'tristate' in my mind is, while the channel is generating 

1 0 1 0 

it will 

drive 1 on the channel, tristate, acquire the data on the same channel 

drive 0 on the channel, tristate, acquire the data on the same channel

drive 1 on the channel, tristate, acquire the data on the same channel

drive 0 on the channel, tristate, acquire the data on the same channel

So by this way, the data will be correctly acquired as 1 0 1 0, but not 1 0 1 1 or something else.

But the 'tristate' function in PXI 6552 is actually not working by this way. It is by cycle. And I have misunderstood that tristate between cycle would help. 

From the tristate cycle by cycle as prompted by Keith, I understand that this features is actually generating the "Z" without having to put "z" in the pattern. It won't help in my case.

Anyway, thanks to Ryan n Keith. Any comments are welcomed.

		drive enable
		0	1
compare enable	0	Z	0/1*
	1	L/H*	Error
*This value is determined by the corresponding bit in data.

[Ryan_M]

Engwei,

For the sake of completeness, here's the excerpt from the help file for NI HSDIO...

Digital Logic States

Digital Logic States

Test engineers can choose from a number of different digital I/O instruments with a range of features for communication and test applications. Beyond the basic capabilities of driving a digital pattern of 1's and 0's, digital instruments often support waveforms that can include some or all of the logic states shown in the following table.

	Logic State	Drive Data	Expected Response
Drive States	0	Logic Low	Don’t Care
	1	Logic High	Don’t Care
	Z	Disable	Don’t Care
Compare States	L	Disable	Logic Low
	H	Disable	Logic High
	X	Disable	Don’t Care

The six logic states control the voltage driver and, if supported, the compare engine of the digital tester on a per clock cycle basis. The Drive states specify what stimulus data the tester drives on a particular channel or when to disable the voltage driver (referred to as the tristate or high-impedance state). Compare states indicate the expected response from the DUT. These six logic states make it possible to perform bidirectional communication and real-time hardware comparison of acquired response data.

The NI 655x digital waveform generator/analyzer supports all six logic states shown in the preceding table, allowing the device to perform bidirectional stimulus/response test options with hardware comparison.