Yes, the RAM is DDR2 and connected to the processor, not the FPGA. Since the RAM is connected to the processor, it is transparent to LabVIEW and there is no API to communicate directly to RAM.The FPGA I/O levels are fixed at 3.3V for the DIO on the RMC connector. The manual of the sbRIO-9606 specifies that the minimum input high logical level must be at least 2V and may not exceed 3.465V. The sbRIO-9606 does not support importing an external clock to use in LabVIEW FPGA.
FlexRIO has external clocking capabilities as well as DRAM connected to the FPGA. This product may be more suitable to your needs.