digsys-04: Sequential Circuits at the Flip-Flop Level

[edoering]

Introduction

LabVIEW FPGA provides complete support for sequential logic circuits at the discrete flip-flop level as well as the register level. This article presents the LabVIEW while-loop combined with a shift register and equivalent feedback node as direct implementation of a D-type flip-flop, and then illustrates how common sequential circuits such as data registers, shift registers, sequence generators, and counters can all be easily implemented within LabVIEW FPGA.

IMPORTANT NOTE: The VIs described in this article (and linked at the bottom of this document) run on the desktop computer to permit anyone to easily experiment with these circuits even in the absence of the LabVIEW FPGA module or supported FPGA development board. However, the circuits use only those constructs that are available in the reduced palette set of LabVIEW FPGA, and therefore illustrate circuits that can be implemented directly on an FPGA. Two of these circuits (the 8-bit Johnson counter and 8-bit up-down counter) are adapted to target the Xilinx SPARTAN-3E Starter Kit and the NI Digital Electronics FPGA development boards; see the LabVIEW project files linked at the end of this document.

Flip-Flops in LabVIEW FPGA

A flip-flop implements a single bit of memory, and serves as the foundation of digital sequential circuits. FPGA configurable logic blocks contain several flip-flops each; therefore flip-flops represent a significant portion of the FPGA hardware fabric.

A D-type flip-flop stores a single binary value, which is available on the flip-flops Q output. The flip-flop samples its D input periodically when a system clock waveform activates its trigger input, typically on the rising edge of the clock waveform. LabVIEW implements this fundamental storage technique with while-loop structures and a shift register, as well the equivalent feedback node.

The term “shift register” deserves special mention here. In the context of digital circuits and systems, a shift register is an array of flip-flops connected to pass binary values between adjacent flip-flops; it is used as the basis of parallel-to-serial converters and UARTs, for example. In the LabVIEW context, a shift register is a special construct associated with for-loop and while-loop structures that stores a value for the next iteration of the loop. Interestingly, the LabVIEW shift register construct can be extended to store values from multiple loop iterations, thereby directly implementing the shift register known to digital designers. These concepts are covered in more detail later on.

The following video continues this discussion by briefly reviewing the operation of a D-type flip-flop, and then develops the conceptual chain from a flip-flop to the shift register and then to the feedback node that concisely implements flip-flop behavior in LabVIEW FPGA:

Registers

The data register – perhaps the simplest flip-flop structure – contains an array of flip-flops in which all flip-flops connect to a common clock signal. The following video presents the schematic diagram of a data register and then describes six different  ways to implement the register based on the shift register, feedback node, Boolean array data type, and integer data type:

The basic register just described samples it inputs every clock cycle. For most applications, however, the register should only sample its inputs on demand according to an enable control signal. The next video introduces the LabVIEW “Select” node that implements a 2-to-1 MUX to select between the presently-stored value and the new value:

Shift Register

The basic shift register contains only flip-flops and wires. The next video details the construction of an 8-bit register that shifts the stored bit values one place to the right on each clock cycle; a serial data input provides the value to be filled into the left side of the register:

Universal Shift Register

A more flexible shift register design allows the stored value to be updated all at once from a parallel input value, shifts only on demand, and provides for both left shifting and right shifting. The next video details the design of a 4-bit universal shift register controlled by three signals called “load,” “shift,” and “direction;” a specialized 4-to-1 MUX implemented by a subVI reduces wiring clutter and also illustrates the modular design possible with the LabVIEW subVI:

The 4-bit universal shift register just described does not scale easily to additional bits. For example, a 32-bit version requires an unacceptable amount of development time to extend the diagram. The Boolean array data type simplifies the diagram layout, and offers unlimited scaling for more register bits; the next video describes this technique to implement an 8-bit universal shift register:

Johnson Counter

The Johnson counter, also called a switch-tail counter, is a classic flip-flop circuit based on a shift register with a feedback connection between each end of the register. Johnson counters produce a characteristic sequence of binary patterns that repeat once every 2N clock cycles, where N is the number of flip-flops; these counters provide a space-efficient means to divide down a clock signal to a lower frequency. The following video shows two methods to implement the Johnson counter, one based on feedback nodes and the other using the while-loop shift register:

Sequence Generator

Occasionally digital systems designers require a circuit that generates a fixed pattern of periodic waveforms. The sequence generator consists of a data register and a customized next-state decoder, and is a common topic in the early sequential logic chapters of digital systems textbooks. The following video shows how a case-structure quickly implements the next-state decoder logic for an arbitrary numerical sequence:

Up-Down Counters

Up-down counters find many applications in digital systems, including event counting and time measurements. As described in digital systems textbooks, up-down counters consist of a data register and an adder/subtractor circuit to form the next state. The following video describes two methods to implement the up-down counter, one based on Boolean arrays and the other based on integers:

Block Diagram Editing Tips for While Loops, Shift Registers, and Feedback Nodes

The following video covers the essential block diagram editing techniques for while loops, shift registers, and feedback nodes essential to creating your own designs similar to those described in this article. The single-cycle timed loop is also presented; this structure causes the circuit to operate at the system clock frequency (50 MHz on the NI and Xilinx FPGA boards mentioned in this article).

Conclusion

The LabVIEW implementations of a variety of common sequential circuits including data registers, shift registers, and counters presented in this article demonstrate the ability of LabVIEW to serve as a platform for the digital systems course laboratory.

[Dr Hamid]

Hi,

Why there is no video on this page!?:(

Thanks

[edoering]

My apologies for the long delay... I did not see your comment and was unaware of the problem with the videos until quite recently. Everything is working fine now.

[rahb]

Hi,

In all examples, the feedback node is controlled or clocked by While loop clock. is it possible to provide digital clock as input source to control the flipflop or feedback node. I am not able to find anything on that. Can you please share the link if there is something available for this.