digsys-01: LabVIEW FPGA in the Digital Circuits and Systems Curriculum

[edoering]

Introduction

LabVIEW FPGA offers a completely new design flow for FPGA targets. The graphical dataflow paradigm and LabVIEW programming environment offer many advantages over traditional HDL-based design flows, not only in terms of design entry, but for simulation, real-time debugging on the target, and host-to-FPGA communications. LabVIEW FPGA supports most aspects of traditional design flows, and can therefore be used as a “learning scaffold” from traditional digital circuits and systems concepts and design entry methods to the more effective graphical dataflow programming paradigm. However, faculty and students need learning materials to guide their transition from the traditional methods to the LabVIEW FPGA approach.

Subsequent articles in this series designated by the prefix “digsys-NN” present a set of reference designs and techniques accompanied by video-based discussion and explanations that cover a standard first-semester introductory course in digital circuits and systems. The reference designs illustrate basic and intermediate LabVIEW FPGA coding techniques and present example applications designed to motivate student interest in further study of digital systems. In addition, an IP library with examples provides immediate access to peripheral devices on the Spartan-3E Starter Kit board (provide URL) (rotary knob encoder, LCD, VGA, and switch debouncer) and the National Instruments Digital Electronics FPGA board (provide URL) (LED display and switch debouncer).

This article describes the motivation for using LabVIEW FPGA to support the hands-on activities of an introductory digital logic course as well as subsequent courses in digital systems, and details the advantages of LabVIEW FPGA compared to traditional laboratory CAD tools.

Motivation

FPGA development boards have become increasingly affordable and the associated CAD tools are available for free (such as Xilinx Webpack) or at low cost. At Rose-Hulman, students taking their first digital logic course are highly motivated by hands-on projects with FPGA development boards that turn lecture concepts into reality. The current tool chain at Rose-Hulman has been optimized as much as possible, but many students are still challenged by the number of disparate tools to learn and the often undecipherable error messages that appear during debugging. Moreover, while expressing a design concept in a hardware description language (HDL) such as Verilog  or VHDL undoubtedly offers efficiencies in some aspects of design entry and simulation, embodiment of the design as pure text creates a disconnect between the embodiment and the associated concepts which are inherently visual in nature: gate circuit schematics, state diagrams, and system block diagrams.

LabVIEW FPGA offers a completely new way – graphical dataflow programming – to implement a design concept on an FPGA target. Provided the design can be expressed with the reduced palette set of LabVIEW FPGA (string functions are not available, for example), capturing the design in LabVIEW FPGA is essentially identical to writing a VI intended to run on the desktop. Running the VI produces a set of VHDL files which the Xilinx ISE synthesis and place-and-route engine automatically synthesized to an FPGA configuration bitstream file, which is subsequently transferred to the FPGA development board. The VI front panel appears on the desktop, and the VI itself executes on the development board. The USB cable facilitates ongoing communication between the FPGA and its front panel.

LabVIEW graphical (“G”) coding supports a wide variety of coding styles, including hardware-oriented techniques such as gate-level circuit schematics and register transfer level (RTL) hardware as well as conventional LabVIEW software-oriented techniques such as for-loop structures and sequence structures. The LabVIEW “VHDL Node” also provides a mechanism to incorporate VHDL code directly into the design.

Advantages of LabVIEW FPGA

Major advantages of LabVIEW FPGA over traditional HDL and CAD tool methods include:

• Efficient design entry – Can often express a given design concept more quickly and concisely
• One tool, many targets– Effort invested learning LabVIEW FPGA carries over to LabVIEW for desktop applications as well as embedded targets such as the ARM microcontroller and National Instruments Compact-RIO product; this is not true for other FPGA design entry tools
• Rapid design verification– A design concept can be quickly prototyped on the desktop computer, eliminating the need to wait for rebuilding the FPGA configuration file.
• FPGA visibility– The link between the FPGA target and its front panel on the desktop computer during runtime offers high visibility into the FPGA, simplifying debugging considerably.
• FPGA pin assignments handled automatically– Since LabVIEW FPGA knows the target board peripherals, FPGA I/O connections amount to point-and-click rather than the error-prone manual entry of a pin mapping file
• Unified development environment– Everything necessary to enter a design concept, simulate it, and then implement it on the FPGA target exists in one application, reducing the effort needed to learn and manage multiple vendor tools
• FPGA and desktop VI communication– Provides the FPGA with access to desktop resources such as data files and network; the VI front panel can also serve as an alternative to a custom-made hardware interface, or can serve as a prototype for such hardware
• LabVIEW FPGA promotes “learning by scaffolding”– Overlap with traditional methods (gate schematics, truth tables, Boolean logic, VHDL, register transfer level (RTL) systems and controller/datapath systems) permits someone new to LabVIEW to start with familiar design entry methods and then make the transition to graphical dataflow programming paradigm

Nearly all laboratory learning outcomes for traditional digital logic course following conventional textbook can by supported by LabVIEW FPGA:

• LabVIEW FPGA supports the full range of traditional hardware design implementations, including gate-level schematics, higher-level combinational devices (MUXes, decoders, encoders, adders, subtractors), memory (ROM, RAM, FIFO), flip-flops, state machines, and register transfer level (RTL) systems (controller, datapath)
• LabVIEW FPGA inherently supports parallelism and can directly translate a system-level block diagram; each block becomes a while-loop structure
• Testbench methodology is supported, and desktop simulation rapidly verifies a design
• Waveforms and timing diagrams can be created to visualize circuit activity, however, the waveform display is not as sophisticated as that offered by conventional digital circuit simulators; in LabVIEW FPGA the focus shifts away from producing and interpreting waveforms to verify functionality, and concentrates instead on direct observation of functionality
• Students and faculty brand new to LabVIEW will feel less overwhelmed by the comparatively small palette set of LabVIEW FPGA

[Tarek_Safwan]

Hi;

Is there any complete Manual which includes all the Digsys series, with all the necessary files, so that it can be used as a complete Lab Manuals to be used in universities??

Looking forward to your valuable reply

Thank you

[edoering]

The table of contents http://decibel.ni.com/content/docs/DOC-6825 lists everything in one place. The materials are only available as online documents here in the Developer Zone Community.