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PCI-6602 Generates Finite Pulse-Train Generation Per 7 Millisecond Though Card'Interrupt

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1.Can the 6602 generate Finite Pulse-Train every 7 Millisecond, and the frequency and duty cycle of the pulses produced in different times are different. If the anser is yes, how can I achieve it(my programming language is c/c++)?

2.Can I cooperate with two counters, counter A is used to generate pulse train, counter B generates GATE signal, when GATE signal is activated, counter A has pulse train output, when GATE signal is low, counter A has no pulse train output? How can I realize the synchronization between gate signal and output pulse ?

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What you're looking to do is definitely not a *natural* application for the 6602.  It may not even be possible, depending on some further details of your timing requirements.

 

Variable pulse timing could be handled much more naturally with a newer board such as the PCIe-6612 or an X-series MIO board.  If at all possible, I'd urge you to implement this on a newer board that can support the timing requirements in hardware.

 

 

-Kevin P

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I mean in the first 7 Millisecond,the 6602 generates  Finite Pulse-Train,in this 7 ms,the frequency and duty cycle of pulses are constant.  in the second 7 Millisecond,the 6602 generates  Finite Pulse-Train,in this 7 ms,the frequency and duty cycle of pulses are constant. But the first 7 milliseconds and the second 7 milliseconds have different pulse frequencies and duty cycles.I don't know if I have a clear description.

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Thanks

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@十三香 wrote:

I mean in the first 7 Millisecond,the 6602 generates  Finite Pulse-Train,in this 7 ms,the frequency and duty cycle of pulses are constant.  in the second 7 Millisecond,the 6602 generates  Finite Pulse-Train,in this 7 ms,the frequency and duty cycle of pulses are constant. But the first 7 milliseconds and the second 7 milliseconds have different pulse frequencies and duty cycles.I don't know if I have a clear description.


Yes, you're being clear, that's what I thought you meant.  The details that aren't quite clear are:

1. Should this be acting like a retriggered operation where each 7 msec burst of pulses is triggered by an external signal?   Or does your app get to control the timing of these 7 msec intervals?

2. Each set of pulse bursts will last less than 7 msec, right?   What's the maximum time spent pulsing?  (This defines the minimum time available to get ready for the next trigger.)

 

Let's first address the easier case where you get to control the timing of the 7 msec intervals.

 

Each window of 7 msec needs its own distinct set of pulse train parameters (freq, duty cycle, # pulses).  On a 6602, you'd need to reconfigure your counter output during the brief interval between the end of  one burst of pulses and the beginning of the next 7 msec interval.  This won't always work because you aren't fully in control of the time this will take.  There's software, an OS, the DAQmx driver and PCI bus traffic that can each affect timing.

 

A newer device (preferably a 6612 or X-series MIO board) would support the ability to predefine a buffer of pulse parameters.  Then it would be relatively straightforward to support distinct finite pulse bursts starting every 7 msec.

 

 

Now let's consider the case where you need to retrigger these pulse bursts in reaction to an external signal that arrives every 7 msec.  Well that's gonna get trickier.   You can probably do it with a 6612 or X-series board but it will take very careful task configuration.

   You'd need to predefine your buffer of pulse parameters such that *each* burst uses the *exact* same amount of total time, let's say 6.5 msec (it *has* to be < 7 msec).  This will require some careful thinking about how you define the first and last set of pulse parameters so that they chain together cleanly.  (Keep reading for a better definition of "cleanly".)

   You would configure this 1st counter task for *continuous* pulse train generation but would also configure it to be pause triggered by a 2nd counter's output.

   The 2nd counter would be configured for retriggerable single pulse generation.  It would retrigger off the external signal and then generate a pulse with *exactly* the same 6.5 msec duration that will unpause the 1st counter task exactly long enough to issue one complete burst of finite pulses.

 

See, it gets complicated, but at least it's probably *feasible* with a newer board.

 

 

-Kevin P

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"You would configure this 1st counter task for *continuous* pulse train generation but would also configure it to be pause triggered by a 2nd counter's output.

   The 2nd counter would be configured for retriggerable single pulse generation.  It would retrigger off the external signal and then generate a pulse with *exactly* the same 6.5 msec duration that will unpause the 1st counter task exactly long enough to issue one complete burst of finite pulses." 

1. As you said,can the 6602 use two counters to realize the function?

2.I mean 2st counter  pauses the 1st pulse train generation?  

3. can the 6612 cards  use the C/C++ Programing language ?

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1.  Yes, the 6602 should support the ability to configure 2 counters to work together this way.  As mentioned before, the difficulty comes in the need for changing the freq and duty cycle parameters at exactly the right time.  These changes will depend on software timing, which is prone to variability and uncertainty on most OS'es.  You probably won't be able to do a perfect job of getting the timing exactly right every time.

   If your app & system can tolerate these occasional timing misses, this approach may still work for you with the 6602 you already have.

 

2.  Yes, 2nd counter output can pause the 1st counter's output on a 6602.

 

3. Both 6602 and 6612 could be programmed with the same C/C++ DAQmx driver API.  Usually the exact same code could be used with either board, unless you were using one of the relatively new features of the 6612 that the 6602 hardware doesn't support.

 

 

-Kevin P

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  As you mentioned before,“ the 6602 should support the ability to configure 2 counters to work together this way.”

1.Can i control the 1st counter  that generates the  finite pulses, for example,18 complete cycles of pulses in the active stat of the 2st counters?  

2. The number "18" maybe a number from 1 to 99.

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 As you mentioned before,“ the 6602 should support the ability to configure 2 counters to work together this way.”

1.Can i control the 1st counter  that generates the  finite pulses, for example,18 complete cycles of pulses in the active stat of the 2st counters?  

2. The number "18" maybe a number from 1 to 99, this number can be specified by the program according to the machine state. In the process of machine operation, it is a positive integer calculated by the program according to the change of the machine state.

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