NI 9361 FPGA configuration

[Benoit_Marchand_DAM]

Hi,

I am using a counter NI 9361 with a CRio 9040 and Labview 2017 SP1 f3 - NI RIO 17.6 -  NI DAQmx 17.6. I configured the Module in FPGA mode. I based my FPGA code on the example provided with Labview 2017 (NI 9361 Counter Digital Input - FPGA.vi + NI 9361 Edge counting (Host).vi). I slightly modified the configuration of the module in the RT part to run in "Quadrature encoder velocity mode". When I run the VI, the  FPGA get stuck in the initialization phase (the first module property node).

I found a fix which enable the code to run : set the NI 9361 in Real-time resources mode, deploy it and run another RT VI which contains DaqMX acquisition of this module (quadrature velocity mode). When I configure the module in FPGA mode and run  the RT VI the acquisition worked.

I am not able to run the RT Vi every time that I either restart the CRio or change the FPGA Bitfile.

I can run the VI if I disconnect the CRio or close/reopen the project.

Did anyone had similar behavior ? Is there a configuration required at start up in FPGA Mode ? (I looked all the module properties but I couldn't find anything)

Thank you in advance for your help.

[Cdkey]

Hi Benoit_Marchand,

Did you see this document: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000kEpeSAE&l=en-US ?

In this link, there is a VI attached that demonstrates how to calculate the velocity and position of an encoder using a NI 9411.

Maybe, you can modify the example to fit with your module.

Have a nice day!

Clement

[Benoit_Marchand_DAM]

Hi Cdkey,

Thank you very much for your response,

As long as I understood, the NI 9361 have it's own clock (@100 MHz) which allows to directly retrieve the frequency. Therefore I would like have to save as much space as I could on the FPGA for other uses. I investigate a little bit further since the first post and I realize that the counter are working correctly as long as the FPGA only contains reference to NI 9361 module. I am also using an NI 9220 FPGA does not execute anymore as soon as I place a read NI9220 value. In order to track to problem, I made a simple vi that only read NI 9220 on FPGA, and it work correctly. But if I add any function form NI 9361, the FPGA code does not execute anymore. I should rename this post "run NI 9220 and NI 9361 on FPGA". I add those examples in this message. Sorry for the mistake on the problem origin. Did anyone experienced such strange behavior ?  

Have a nice day.

Benoît.

[gregopher]

I have experienced this problem as well.  I could not find a solution and ended up abandoning the FPGA code and making the 9361 a DAQmx device for my project.

I was able to get the example to work sometimes, but it would sometimes hang up as you experienced.

[gregopher]

Any updated from NI on this issue?  This is still causing my team problems and forcing us to NOT USE the 9361 in future project for which the module is an ideal application.

[MIK3F00]

Hi gregopher,

Just came across this thread last week and wanted to chime in. 

We have also encountered this issue over the past couple weeks and have escalated it with NI support. I'll let you know what they come back with. 

Our hardware configuration:

• cRIO-9054
• NI-9361
• NI-9402

We are using the 9361 for two quadrature encoders (ie 2x 3 input channels) and the 9402 for IRIG time-sync, and need to program both in FPGA.

The issue is very similar to what has been described above.

Namely..

• We have an example IRIG code for the 9402 in FPGA that compiles and executes without error
• We have example quadrature code for the 9361 that compiles and executes without error
• When we create an FPGA VI that combines the above examples, the FPGA VI hangs at the first 9361 property node (setting Digital Logic Threshold)

Did you raise a support request with NI directly?

What other hardware are you using with the 9361?

Cheers,

Michael Foo

[gregopher]

I was using a cRIO-9045 chassis with several other modules.  I tried simplifying my application to just a 9361 and a 9220 and I still experienced the issue.  I also tried a number of different workarounds which I can't quite recall at the moment, but they did not result in success.

I suspect this issue will exist with the NI 9326 Frequency Input module as it has a similar API.  I have not tested with this device yet though.

[gregopher]

Michael, any response from NI yet?

[MIK3F00]

Hi Derek,

I have a teleconference with an NI TSE this afternoon and will let you know what the outcome is. 

Cheers,

Mike

[MIK3F00]

Hi Derek,

We have provided NI with examples of the issue and they are investigating the root cause and potential solutions. 

In the meantime, we have been able to get some of our basic examples working by the following methods:

• Compile FPGA
• Manually download FPGA from LV project (right-click on build spec and select download) 
  • Screenshot attached
  • Note that this also works if you run the FPGA in Interactive Mode first (ie press Run arrow)
• Then run RT (host) VI

If you encounter the FPGA freezing, you'll need to reboot the cRIO before re-attempting. 

Note that if you are swapping between two different FPGA VIs, you'll need to manually download the FPGA before running the RT. 

I acknowledge this is only a temporary work around and doesn't really explain the root cause of why this is occurring, and why we've only encountered it with FPGA VIs using the 9361, but for us at least, it allows us to continue development/testing. 

(My suspicions are that it is related to the fact that the properties on the 9361 module counters cannot be edited once the counter has been armed)

I'd be keen to know if you have any success with the above. 

Cheers,

Mike