Is this possible on a PCI-6115?

[Grez]

Hi,

I have a PCI-6115 board with an external clock source running at ~8kHz and I am trying to produce the following outputs using Labview:

1. A frequency divider as a "wrapper" around N (probably 256 or 512) of the clock pulses. 
2. An analog ramp output that starts at the same time as the"wrapper" pulse in (1), has N steps and finishes at the same time as (1).

I've attached a basic diagram of the signals I want. I can produce a ramp output timed using the external clock, or I can produce the "wrapper" using a counter, but I can't do both together synchronously!

Anyone have any ideas?

Thanks

Message Edited by Grez on 04-01-2009 10:20 AM

[Jeremy_T]

Hi Grez

I hope you're having a good day. I just wanted to ask a couple of questions about how you are implementing both the measurement of external source and the generation of the wrapper and ramp.

Is the issue that you are unsure of how to synchronise them in the first place? Or do you get any specific error codes when you try to include both the ramp and the wrapper together? Presumably you are using a counter to measure the external source, and that also both your wrapper and ramp require counters. The PCI-6115 has two counters on it, however if you were to use counters for both the wrapper and the ramp you would require three. Given that the ramp and the wrapper have the same start and stop time, there may be some way we could get round this.

Is there any chance you could attach the code you are using? That way I can take a look at exactly how you are creating the outputs and think about ways we can synchronise them.

Kind Regards

[Grez]

Hi Jeremy,

I've had another go at this and have found a possible fix/workaround, although I still have a couple of queries (see the end of this post). I've attached the code this time so you can see what I'm talking about. The methodology is as follows:

1. Use a counter output (ticks mode, high 256, low 2) to generate the "wrapper". The trick I was missing here was to change the counter active edge from the default (rising) to falling. The trigger is also the tick source, but could easily be another input signal. The counter is started re-triggerable.
2. Create an analogue output for the ramp signal. Sample clock is the same as tick source for the counter. Active edge is falling. Trigger source is the Internal output of the counter (rising edge)
3. Data to be written is generated from a ramp generator between start and end voltages. Assuming the ramp goes from, say, 0 to 1 in 256 steps: delete the first value in the array at position 0 and then add another array (1D) with 3 values (all zeros) to the end of the modifies ramp. This gives a final array of 258 values with the last 3 being zero.
4. Data is written to buffer and the tasks are started. Check for task done every 100ms andthen do errors etc. at the end.

This produces the desired wrapper signal and ramp, both being generated from the same clock source.I have a couple of queries still though:

• I can only run this successfully in Finite samples mode. So for example I can set the ramp samples per channel to 2580 to generate 10 ramps synchronized with 10 wrapper signals. If I run the ramp in Continuous samples mode it works ok for about 1 second and then the ramp goes a fixed amount (~7 clock cycles) out of step with the wrapper signal. How can I get this to work continuously?
• This would have been easy if the analog output could be made re-triggerable. Is there any way to do this?

Thanks for your help.

[Andrew McL]

Hi Grez,

I hope you are having a good day. I have taken over this Service Request from Jeremy. I understand you wanted to know if you could do re-triggerable Analog Ouput; I've attached a document here that details how to do this. 

I had a look at your block diagram and I am wondering if the problems you are seeing are potentially due to 2 things:

1. There doesn't seem to be a DAQmx Timing VI on the block diagram for the Counter task. I would recommend putting one of these in as this may sort out the Timing skew you are seeing.

2. In the report errors VI, the "OK messages + Warnings" constant seems to be wired to the top of the error report. I think its meant to be wired to the 3rd Node down on that VI instead.

3. My final suggestion would be to check all of your Sample Rates and number of Samples.

Please let me know how you get on,

Many thanks,