Generate two CO from one counter?

[Flumen]

Hello,

I have a PCIe-6353 DAQ board, which has 4 clocks available. I am already using all four of them and am now looking for a way to make one of them available for another task.

This is what I would like to do but I am not sure if that is possible:

- ctr 0:  I generate one clock every 10 ms, which is used as trigger signal

- ctr 1   is set up to generate a clock every 10 us. The timing is set up finite output of 1000 samples, retriggerable and triggered by ctr0. This basically equals a constant pulse train

- ctr 2 is doing exactly the same as ctr1 except that a smaller number of clocks is generated.

Since ctr1 already defines the frequency etc,  do I really need ctr 2 to do the same just for defining a different number of output clocks? The only thing that changes beytween ctr1 and ctr2 is the DAQmx timing VI settings.

Thanks!

[Kevin_Price]

What's the bigger picture?  What purpose is being served by these various clock and triggering signals?

Is ctr2 being used as a sample clock for another task, such as AI/AO/DI/DO?   If so, you could probably set the *other* task to be finite and then use ctr1 as the sample clock.

Other notes:

- you've got yourself "line to line" on the timing requirement for ctr1.  1000 pulses with 10 usec period requires 10 msec.  You also want to retrigger every 10 msec.  You might have a problem there -- you need to allow some tiny amount of time to for the triggering circuitry to be re-armed *after* all the pulses have been generated but *before* the next trigger signal.  You have your pulses finishing at *exactly* the same time that the next trigger signal arrives.

- not sure where else you're using ctr0, but can you consider *deriving* ctr0 from ctr1?   I recognize that this could lead to complications for ctr2.

- I haven't done this, but I *think* you could make ctr1 a buffered pulse output task.  With some cleverness, you could define the last pulse to have an extra short time in idle state (or some similar thing depending on your settings for polarity, initial delay, etc.) to allow time for the triggering circuitry to re-arm.

The more you can describe about the purpose and usage of these various clock and triggering signals, the easier it'll be to give better advice.

-Kevin P

[Flumen]

These clocks/triggers are used to trigger AO from the DAQ card and synchronize it with several external devices.

- thanks for the note about the extra time needed when retriggering. I was not aware of it and it actually was/would have been an issue. I changed it accordingly. Thanks!

- ctr0 is the main trigger for other processes. It triggers basically all other counters directly or indirectly.

- My thought was to only use the counter to define one single signal (like 1000 ticks up, 9000 ticks down) and derive two tasks from it which differ only in the sample clock settings. I guess this is not possible - and I did not really expect it.

I came up with a workaround, which requires me to acquire more data than necessary and then cut the acquired data after acquisition. It is not pretty but also not a big deal. It would be still interesting to know if the above mentioned is possible.

Thanks

[Kevin_Price]

Can you describe the purpose and timing relationship of these various signals more completely?  There might be a more direct way to do what you want, but I'd first need a clearer description of what you want.  It may also be helpful if you describe your workaround.  Post code too (preferably LV 2016 or earlier).

In general, a variety of secondary timing signals can be derived from one master.  There might be a better solution available.

-Kevin P