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From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
12-19-2007 04:05 PM
12-20-2007 08:50 AM
If I understand correctly, both the 16-bit data word and the clock signal are being generated as part of an interface to some other piece of equipment. That device is going to read the 16-bit word when it sees your clock's rising edge. Right so far?
You'll definitely need to use the "correlated DIO" feature to give you 1 MHz sample timing. In that mode, you'll be required to supply a sample clock source signal to your digital output task. The most typical way to do it is with a counter pulsetrain task.
Now here's the neat trick part. You can make your pulsetrain to have opposite polarity, so that it's normally high while making a low-going pulse. Then you can make your DO task generate its output on the *falling* edge (which will be the leading edge) of the pulsetrain. Then the clock's *rising* edge (which will be the trailing edge) can come after 1 usec+ of stabilization time to signal the external device to capture your 16-bit word.
Note: you said you want to generate at 1 MHz while also having a 1 usec setup time. These specs are in conflict. With 1 usec setup time and some amount of stable capture time allotted, you'll have to update at < 1 MHz.
-Kevin P.
12-20-2007 09:11 AM