Create output trigger relative to two input triggers?

[bhpowell]

I'm updating a Traditional DAQ application to NI-DAQmx.

The old system uses PXI-6602 boards.  The new one uses PXIe-6614 boards.

Because of limitations of DAQmx, I don't think a straight port is going to be possible. (Details below.)

The problem I'm trying to solve:

I need to measure the time between two input pulses.  Let's call them t0 and t1, and their difference is n ticks.

I need to generate an output pulse at a fixed offset in time before t1 + 2n ticks.

The old application took advantage of a feature in Traditional DAQ that I don't think is present in DAQmx.

The program uses three counters.  One counter is set up to divide the 80MHz clock base depending on the gate.  It is programmed to give a 40MHz clock when the gate is low, and a 20MHz clock when the gate is high.

In Traditional DAQ, you could set up the counter in FSK (Frequency Shift Keying) mode, setting up one duty cycle for gate low, and another for gate high.  That's the part that I don't think can be done in DAQmx.

The output of that counter becomes the source of another counter which counts down at 40MHz and then up at 20MHz.  When you get back up to zero, you've computed the "2n ticks".  You can account for the fixed offset by doing some simple offset of the count of this second counter. (I know that's confusing; I can provide more detail, but I'm not sure it's relevant if I can't shift the clock frequency for the counting.)  You can take the output of the second counter and feed it to a third counter to generate the output pulse when the second counter gets back up to zero.

Any ideas on how to tackle this problem with DAQmx?  I'm open to using other hardware if necessary, or different approaches to my problem.  I like the 6614 because it's pin-compatible with the 6602, and I'm using a bunch of the DIO lines for other purposes.

[Kevin_Price]

Hmmmm.   Wanting to help, but not sure if I can.  At minimum, it'll take some more discussion.

1. As far as I know, not too many people spend a lot of time on the counter/timer forum.

2. So, FWIW, I may be your best shot.

3. I did a fair amount of stuff with counters on desktop 6602 boards under traditional NI-DAQ.  Again, probably not many other people who read this post will be as geezer-ish as me.

4. That said, I *never* did anything with Frequency Shift Keying and don't honestly know exactly what's meant by it.   A quick ni.com search on FSK kept pointing to specialty RF boards.

5. I also don't really understand how your present timing relationships work.  However I do know quite a bit about NI's counter/timers, so if there's a way to get there from here, I'm a pretty good bet to be able to find you a method.

    Can you go into more detail about these timing relationships and dependencies?  Please describe both the idea and also give a concrete example with actual #'s.

6. I wasn't previously aware of the *existence* of the 6614, but if it's pin-compatible with the 6602, I'm guessing it might be the PXIe version of the PXI-6608 complete with high accuracy oven-controlled oscillator?

Ok, your turn....

-Kevin P

[bhpowell]

Thanks for at least trying to help!

Here's a link about the 6614 board.

Here's a snippet from the Traditional NI-DAQ Help file:

Frequency Shift

In this application, the counter is used for generation of frequency shift keyed signals. The counter generates a pulse-train of one frequency and duty cycle when the gate is low, and a pulse-train with a second set of parameters when the gate is high. By default, you get this by using the 20 MHz internal timebase so the timing resolution is 50 ns. While the gate is low, the counter loads pulse spec 1 and counts down to zero for the inactive pulse train. It then loads pulse spec 2 and counts down for the active phase of the pulse train. The counter repeats in this manner. The FSK pulse generation starts as soon as you arm the counter. You must reset the counter to stop the pulse generation.

While the gate is high, the counter loads pulse spec 3 and counts down to zero for the inactive pulse train. It then loads pulse spec 4 and counts down for the active phase of the pulse train. When the gate changes state, the cycle in progress finishes before the second set of parameters are used.

Note that the internal timebase of the 66xx series is 80MHz.  (At least for the 6602 and 6614.)

The FSK counter is set up for a 2/2 duty cycle with the gate low, meaning 2 ticks low, 2 ticks high, which equates to a 50ns pulse train.

When the gate goes high, it switches to 4/4 (or in one case 8/8), giving a 100ns pulse train (or 200ns for the other case).

That counter is used as the source for a second counter, which counts down.  This counter has a gate input to start counting, and an up/down input to specify the direction of the count.  So input pulse number 1 starts the counter counting down, and input pulse number two both starts the counter counting up, and also acting as the gate for the FSK counter.  This has the effect of causing the counter to count up at half (or a quarter) of the rate at which it counted down.

So let's ignore the timing offset for now, and say that the second counter starts counting down from zero when the first trigger occurs.

Say, then, that 1 microsecond later, the second pulse arrives.  The counter will be at -20.  (Twenty 50ns pulses in 1 us.)

Now, the counter will reverse direction and count from -20 to 0, but it will take 2us (or 4us) to get there, because the first counter's pulse train clock has been divided.

You can ignore the third counter for now, but it's used to monitor the zero crossing of the second counter.

Does this help?

To add in the timing offset, you can start the second counter at a positive number, so that the negative to positive zero crossing happens earlier than it would otherwise.

[bhpowell]

This looks promising, but I'm not sure if it works with the 66xx series boards...

https://forums.ni.com/t5/Example-Code/Implement-FSK-with-X-Series-and-DAQmx/ta-p/3503175?profile.lan...

When I get the hardware I ordered, I can try it out.

[Kevin_Price]

[Edit:  I had my reply below queued up for quite a while and finished before seeing your followup post.  It looks like the link is pretty much showing you the "how" of what I tried to describe in a bunch of words.  Give it a try!]

There are certain things the PXIe-6614 spec sheet doesn't declare explicitly, but I see clues that suggest the following to me:

A. the device is designed around the STC3 timing chip (similar to the 6612, and the 63xx X-series boards)

B. Therefore, it supports change detection on digital port 0

C. And therefore it also supports buffered pulse train output.

So I *think* those things make a way to produce a similar effect as FSK.  It isn't something I've tried and verified and it might seem a little weird, but bear with me.  

1. You'll set up a helper DI task based on change detection.  You'll make it sensitive to both rising and falling edges of the signal you presently use as the "gate" for FSK.  And then you'll be making use of an internal signal known as the "change detection event" (search ni.com and the forums for more info) by the next task I describe.

2. You'll set up a buffered CO task.  The buffer of pulse specs will alternate between your two different pulse rates, either 2/2 Ticks or 4/4.  And you'll designate the device's internal "change detection event" as the sample clock signal.

3.  The result should be that each time the external "gate" signal changes state, an internal change detect pulse will occur, which in turn makes the pulse output task advance to the next set of pulse specs in the buffer.

4.  The main thing left is to use a start trigger if needed to make sure the correct pulse specs get initiated by the appropriate digital transition of the gate signal.

5.  All this covers merely the FSK counter, but I'm assuming your other 2 can be transitioned to DAQmx in a more straightforward way.

-Kevin P