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I2C Digital Waveform (IDW)

Hi Anne -

 

I'm glad it works. 🙂  Since this approach is based on using an oversample clock to place the edges of the waveform, you'll never be able to approach 0 ns without a Terahertz sample clock.  (This would give precision in the picosecond range.)  But I've never heard of an I2C test application that requires such precision, given the low bus rates of this protocol.

 

There is a control on the Close VI named "Sample quantum (min 1)".  That value represents the waveform quantum for whatever hardware device you're working with.  (For your 655x board, the value is 2 samples.)  WIre a constant of 2 to that control, and the waveform output from the VI will always have an even number of samples in it.

 

Full documentation for the VIs in the IDW library can be found on in the DevZone article you downloaded the library from.

David Staab, CLA
Staff Systems Engineer
National Instruments
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David,

 

I have another question about I2C timing.

 

I noticed that SCL rates impact tSU,DAT from oscilloscope images. When SCL rises, actual tSU,DAT is measured smaller while tSU,DAT input stays the same in the front panel.

SCL is constructed by 250 sample clocks per bit. A 200k hz SCL requires 50M hz sample clock rate, 400K hz one requires 100M hz. 

 

Do you see how SCL could impact timing?

 

Anne

 

 

 

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Hi Anne -

 

What sets of timing parameters are you inputting to the Init VI in the I2C timing (ns) cluster to create this effect?  The Init VI generates all the waveform timing; you may want to study it to understand how the parameters are linked and how they generate the Timing (ticks) cluster.

David Staab, CLA
Staff Systems Engineer
National Instruments
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David,

 

1. I think the reason I2C timing being related to SCL rate is because SCL in my program is constructed by dynamic sample rates. Lower SCL requests lower sample rate, and hence lower resolution. Please let me know if you think there are other causes.

 

2. I installed IDW 1.1.0. But Close.vi still does not have the sample quantum note. Don't know why.

 

3. To measure tSU,STA, I replaced 2 vis in read command P(stop)+S(start) with Sr(repeated start). However, SCL didn't rise for its part in Start. What did I miss?

 

Thanks,

Anne

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Hi Anne -

 

1. No, I don't see any other reason for the behavior you're describing.  Is there a project/system requirement that's causing you to change the sampling rate with the bus rate, instead of just running at a fixed sample rate all the time?  (The most common reason is an on-board memory limitation, but if you have enough memory for all your waveforms I recommend just keeping the sample rate fixed.)

 

2.  I'm not sure why you don't see it.  Here's what I see when I downloaded and installed the library into LV86 on a fresh machine:

 

 

3. Actually, I think you found a bug. Smiley Sad  The Stop (P) bit leaves the [SDA, SCL] lines in the [Z, Z] state, so that when a Start (S) bit is used subsequently, the SDA line can be pulled low while the SCL line stays high.  But the ACK bit leaves the lines in the [Z, 0] or [0, 0] state.  This means that when the SCL line is never released prior to a Repeated Start (Sr) bit.  That leads to a syntactically incorrect Sr condition on the bus.

Message Edited by David S. on 03-24-2009 09:28 AM
David Staab, CLA
Staff Systems Engineer
National Instruments
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All -


Here's a screenshot of the modification to Add Start Condition.vi that you'll need to make in order to use a Repeated Start (Sr) condition in IDW 1.1.0.  It forces the VI to release the SCL line as part  of the setup for a Sr condition.  A fix for this bug will be included in the next release of IDW.

David Staab, CLA
Staff Systems Engineer
National Instruments
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Hi David,

 

I installed IDW library 1.1 in 11/08, but Close.vi with sample quantum option is not updated. Not being able to reinstalling, can you give me a copy of source file so I can manually update it in my system?

 

Thanks,

Anne

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Hi Anne -

 

Sure thing.  I'm sorry the installer isn't working properly; it's a simple LV Installer that I created in the LV Project.  Here's the VI.  I hope you don't have any linking issues with the library.

David Staab, CLA
Staff Systems Engineer
National Instruments
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Thanks, David

 

The installed file has one error: Unbundled by name: Contains unwired or bad terminal.

 

In block diagram, 5 elements are selected after I2C waveform info, but "Compare types" and "Compare locations" do not belong to I2C waveform info. Is this a mismatch?

 

Anne

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Hi Anne -

 

Those two values are part of IDW.lvlib:Waveform info.ctl.  Open your copy of the typedef (in the \_Typdefs\ subfolder) and verify that they're in that cluster.  If not, then you have some old code (from the 1.0.0 release, I believe). In that case, I recommend doing this:

 

  1. Use Add/Remove Programs to uninstall the component
  2. Navigate to your <labview>\user.lib\ folder and manually delete any folders named "I2C Digital Waveform" or "IDW".
  3. Navigate to your <labview>\examples\ folder and do the same.
  4. Reboot your computer
  5. Install the current version.
Let me know if THAT doesn't fix the problem.
David Staab, CLA
Staff Systems Engineer
National Instruments
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