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CompactRIO Waveform Library

Hi,

 

I have been trying to add additional module channels to this Project however although I can edit the front panel to change the 'channel info' even though I save the RT VI whenever I open it again it has not saved. I have tried editing the Typedef but the same thing happens. I have added the relevant modules to the FPGA VI and changed the number of channels to 8 and this seems to have compiled OK.

 

I am relatively new to LabVIEW and have been looking for an example to run both NI-9223 and NI-9237 C-modules and this one seems to fit the bill.

 

Any guidance would be appreciated.

 

Many thanks

 

Bob

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Message 91 of 115
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I am not sure if I got u right, but: Are you missing a Rightclick onto the Channel Info Frontpanel Control and -> Data Operation -> Make Current Value Default?

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Message 92 of 115
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Hi,

 

I tried what you suggested however that hasn't worked.

 

My problems is as follows:

 

I have amended the FPGA VI to include a DSR module (NI-9237) and an SAR module (NI-9223). The DSR is currently Mod 2 in the chassis (NI 9155) while the NI-9223 is Mod 1. I have associated the FPGA IO node with each of the relevant modules and used separate IO nodes for each type of module and then added the outputs together as recommended in the Application. This VI seems to compile OK though I probably need to tweek the error handling to cover the SAR example as it currently just uses the error handling from the DSR [FPGA] VI.

 

The main issue is with the front panel of the RT/Host; in particular Areas A and B (see image below):

 

LabVIEW DSR+SAR VI.jpg

 

Currently it shows the 4 channels from Mod 1, however I would like to add the 4 channels from Mod 2.

 

If I change the 'channel config' typedef and 'make current value default' and save the Type Def I get the following:

 

LabVIEW ChannelConfig Type Def.jpg

 

In this case the last 'current value' has been used for the default even though I changed each of the previous (greyed out) channels to Mod 2/ai0, Mod 2/ai1 etc.

 

Also as can be seen in Area B in the 1st image, the last 4 items are plot 5, plot 6 etc rather than Mod 2/ai0, Mod 2/ai1 etc.

 

Any pointers in how I can change this would be much appreciated.

 

Kind regards

 

Bob

 

 

 

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Message 93 of 115
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Jeff,

 

First off, your application is awesome and informative!  Thanks for your had work.

 

Have you revisited the idea of adding analog waveform output functionality to the cRIO Waveform Library?  My applications require simultaneous AI-AO.  I have successfully implemented the shipping example "Multi-function synch AI-AO" or something like that for DAQmx.  I have a need to duplicate this capability with cRIO and I wanted to check in with you to see if you are on the fence about adopting this functionality.

 

Also, do you have more documents similar to the "Customizing the FPGA VIs.pdf" that is included in the Example cRIO Waveform Project?  This one has proved helpful in gaining a grasp of RT-FPGA programming structure.

 

 

 

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Message 94 of 115
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Hi all,

for some reason, I am missing the example projects that I see in the description. Anyone an idea?

I use Labview2013, installed the package with the package manager without any issues.

Thank you.

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Message 95 of 115
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I think the example project has been converted into a Sample Project in the Create Project dialog.

 

criowaveformexample.png

authored by
Christian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX


  
Message 96 of 115
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Hi,

 

I am trying to get my NI9237 (Analog Delta Sig Half Bridge Strain) to read continuously using the cRIO Waveform Reference Application, specifically using the RT Cont Acq VI that you used. I get a similar timeout error  that you mention in your FPGA Part item 3) and wondered how you solved it. I have tried increasing the timeout to the DMA and changing it to -1 but get the same error.

 

I realise it is nearly two year ago when you posted your reply but would be grateful for any advice.

 

Kind regards

 

Bob

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Message 97 of 115
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My recent post refers to SEGIO's post of ‎04-11-2013 10:29 AM

 

Bob

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Message 98 of 115
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Tring to add Temperature (9211) module to FPGA. Getting underflow error on the RT vi. Does the loop for 9211 look ok?

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Message 99 of 115
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Can I also see how you are configuring, starting and stopping the 9211?  It is a Delta Sigma module so it needs explicit sample rate, start and stop commands.

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Message 100 of 115
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