Certification
Sample Exam Solutions for Review
The result looks pretty efficient, apart from copied states.
I have no idea how you created it, or how to increase speed.
Auto tool and quick drop increase speed, but you probably use at least the auto tool. QD + ctrl+W would wire all those queue functions together automatically, saving a lot of time.
In my experience, the state machine cases, especially the copies, ruin your efficiency. Copying and then revising them for changes should be avoided. Not only is this terrible for efficiency, it's also a source of mistakes and wiring mess.
BTW I would recommend to never name a queue. It's a mistake to do so, as it effectively creates a global recourse. I've seen it go wrong, where libraries used the same queue names. But it wouldn't matter for the CLD.
Search LabVIEW like a graph! 
@piterx wrote:
Could you review my ATM CLD sample exam attempt.
Thank you in advance
I think this would be instant disqualification, but I might miss something.
When I open the project, I see the Main.vi. I open it, and it can't find a VI (account opperation.vi).
Now I see there's an Automatic Teller Machine (ATM).vi. It is not in the project! I think the name of the top level VI is provided. Stick to it.
You have to take care about that. An examiner has to and will follow the rules and procedures. It's broken (for me) so 0 points.
When submitting your solution, close it and open it at least once.
I thought I'd evaluate the rest of the code, assuming it's in Automatic Teller Machine (ATM).vi. But that one is empty.
The main.vi has lots of crossing and bended wires, objects overlapping wires, etc.:
That will be tested automatically, and you'll loose points on that.
You can wire the error wire directly to Boolean operators, no need to unbundle.
The documentation looks great. Just don't let the comment overlap enums...
@mourad_FAKHFAKH wrote:
Hello everyone,
Preparing for the CLA exam, here is my CLA elevator and ATM exam attempts. (LabVIEW 2019)
Nothing fancy, a classic architecture using FIFOS to communicate between modules.
I have completed this attempt in 3h15 as it was not the first exam attempt.
Thanks for any feedback. I hope it can also provide some ideas about modules implementation.
Best regards,
Mourad FAKHFAKH, Certified LabVIEW Developer
Are you still looking for feedback or did you do the exam already?
@cyongjed wrote:
Hi Forum Members,
Appreciate if you could help me vet through the boiler controller VI that I have done up. I have uploaded the file in LV15 version. Do give me feedback and comments if anything is lacking, appreciate it!
Thanks!
Are you still looking for feedback or did you already do the exam?
Not sure why this isn't picked up, I'm usually not the only one reviewing (and really don't want to be).
Hi Wiebe,
I have sat through the CLD exam and obtained my certification. Appreciate your efforts here!
Regards,
cyong
@cyongjed wrote:
Hi Wiebe,
I have sat through the CLD exam and obtained my certification. Appreciate your efforts here!
Congratulations!
