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Sample Exam Solutions for Review

Hello MeCoOp,

 

I don't want to force you to use the high level VI's, but doing a mix of both can be a bit annoying (for yourself Smiley Happy ) during the CLD.

It makes your CLD more prone for "little errors".

One examples:

- Accidentally interchanging line feeds with carriage returns or eol constants.

 

Please let me know if you find it Smiley Happy

Kind Regards,
Thierry C - CLA, CTA - Staff R&D Engineer, RF Semiconductor Test - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. Smiley Wink
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Hello,

 

I am preparing the CLD exam. I did a timed practice today, 3.5 hours from scratch (the real exam may costs longer, since I have already read the problem and designed some functions in mind before the practice)

I post my solution here. Please help me to check.  Any comments and suggestions will be appreciated!

 

PS: programmed in LabVIEW 2012

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Message 32 of 503
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Hello phyyu,


I only had the chance to have a quick glance at it, but after a test it seemed to function correctly (so that's already most of you functionality points).
Can you also link to the pdf with the requirements document you used as starting point?

Then I can test all requirements. Now I'm just testing based on what I remember of it.

 

First thingthat popped into my mind:

Did you use the VI Analyzer on your code?

 

Other remarks after the first look:

- I like that you labeled most of your wires 

- I also like that you provided descriptions for subVI's

- You didn't provide a comment for each case in your subVI's (even error cases should have a comment in them).

- Not all controls of subVI's have descriptions. (example: step in/ step out of Run Selector VI

- You preliminary code (reinitialization invoke methode) has a wire that goes from right to left. Should not be there and the VI Analyzer would automatically tell you about this.

 

Some smaller remarks:

- There are some unecessary bend in certain wires. try to limit/remove those.

- Also not all descriptions in case are equally complete and also I found (at least) 1 case  where you didn't put any comment in at top level.

 (Ex: False case inside the Running Case)

- If you have the same data being used ins everal VI's after each other, then try to apss it through the subVI instead of around it.
I'm talking about the Run Selector and Zone Selector subVI's.

 

One major thing missing:

I don't seem to find a reasoning that explains why you chose this design pattern.

I think this is still one of the thing that is explicitely mentioned on the Requirements Document.

 

You are for sure on the good way and with a little more practice (also makes your programming faster) you should get there.

 

One thing I always advise everyone:

Try all example exams and when you're done retry them a second time.

 

When you're done with that, then you can always ask other users for programming challenges (eg. create your own calculator)..

Also a good idea would be to try the tips they give you in the documentation about the CLD.

Kind Regards,
Thierry C - CLA, CTA - Staff R&D Engineer, RF Semiconductor Test - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. Smiley Wink
Message 33 of 503
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Hello Thierry,

 

So appreciate for your reply, really helpful. I attached the requirement document I used for this practice.

I didn't use the VI analyzer, is it required in the CLD exam? (Actually, never use it before...)

I think the simple state machine is good enough for the exam, right?

 

Thanks again!

 

Yue

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Message 34 of 503
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Hello Phyyu,

 

As long as you can meet the requirements with it it's ok.

If you cannot meet the requirements with it, then you should use another Design Pattern.

This all depends on the application you have to make.

 

I know this is a vague answer, but it realy depends from application to application.

 

You don't have to use the VI analyzer, but you should at least try it.

The VI Analyzer can automatically analyze your VI's and check if you did not follow certain style guidelines.

Just try it once on your test exam and you'll directly see why it's useful Smiley Happy

 

 

Kind Regards,
Thierry C - CLA, CTA - Staff R&D Engineer, RF Semiconductor Test - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. Smiley Wink
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Message 35 of 503
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Thanks for reply.

 

Could you please show me where the VI analyzer is? In the tools menu? I coun't find it.... is it an add-on tool kit?

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Message 36 of 503
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It should be as illustrated in the picture.


It could also be that it's not covered under your license.

Kind Regards,
Thierry C - CLA, CTA - Staff R&D Engineer, RF Semiconductor Test - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. Smiley Wink
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Message 37 of 503
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Hello Thierry,

 

It is not there... Not include in the version I used. But thanks anyway.

 

Yue

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Message 38 of 503
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I did another practice of ATM today, donot have enough time to finish the all functions. (Only left menu has been done in the 4 hours limit) 

And the enter button has been pressed twice to get the right function response... (I think the functional grobal variable donot updated at the begining? Could anyone show me the way to solve it?)

I also add a line at the end of the accounts file to determine whether the account number user entered exist. Is it ok to do this to the file in the exam?

 

Please check and help with the questions. Thanks soooo much!

 

Regards,

 

Yue 

 

 

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I'm posting my sprinkler and ATM sample test solutions for review. I've worked the boiler and carwash samples as well, but those are fairly easy in comparison to these two (in my opinion). The attached projects show my best effort (well, maybe "good" effort) at following recommended documentation and style guidelines. I think the functionality is 100%. These represent about 3 hours of effort on the sprinkler and 3.5 on the ATM. Please let me know where I can improve.

On thing I'm questioning in particular: Are feedback nodes on the right side of the loop a no-no? They really help clean up alot of the cross-loop shift register wires but VI analyzer has a heart attack about wires running the wrong direction and inputs on the right side of a case structure, blah blah blah...


I would like to know if these solutions are up to par for passing the CLD, i'm aware that the actual CLD is a little more involved, but I'm looking for general pointers such as "don't do this and that, you'll fail" or "looks good, keep on keeping on". Thanks for the help!

 

 

Philip
CLD
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