Having troubles to get my FPGA design to compile for the target.
Error is overuse of DSP blocks. 64 available on target..
Do i have to minimize the number of multiplier blocks?
Or can i somehow multiplex on DSP between several variables minimixe DSP use?
Solved! Go to Solution.
How is it going with your application - did you manage to compile the code?
Suggestions for eliminating the problem:
* Reduce the amount of logic in the VI
* Reduce the number of multiplications, FIFOs, and/or amount of memory on the block diagram
* Reduce the number of objects on the front panel
* Change arbitration settings
* Use Timed Loops instead of other loops
* Use Timed Loops for resource-intensive sections of the block diagram that
do not require any looping
Other thing to try, is to create a new simple project and see if that can compile. Also, try to minimizer your original FPGA as much as possible, just to see if it eventually will compile.
Also, feel free to attach your code, and I can try to compile the code. I do not have the same hardware, so I cannot actually execute it, but I will be able to compile the FPGA code.
FPGA High Speed Math Multiplier must be set to LUT and not AUTO, as this will use DSP, and not AUTO to LUT if there is too few DSP's.
This will lower DSP usage, but increase LUT use.