MyRIO simple code compilation FPGA

[pawhan11]

Hello,

I am new to FPGA and I want to compile some simple code. I know that myRIO comes with default FPGA configuration so I want to create new one and compile it. Lets say that I want blinking LED. So I create new VI on FPGA and here is simple code:

then I add it to build and start compilation

As compilation goes it says that it will use 30% of FPGA resources:

Why is that? Whole compilation on cloud server takes more than 20 minutes. I have seen some example videos on CRio FPGA and that simple code should use no more than 2% of resources and shuld compile in 2 to 3 minutes.

What I am doing wrong?

Thanks in advice

[Kristoff2]

Hey Pawhan11,

There are two main reasons for the FPGA resource consumption.  First is that the FPGA on the myRIO (Zynq Z-7010) is relativly small compared to some other NI targets you may have used.  The second reason that even a simple FPGA application takes ~20% of the FPGA fabric is because some of the FPGA fabric is already being used for other purposes.  For example some NI Real-Time targets implement UARTs, RS232 or even ethernet in the FPGA to ensure consistency between devices. 

Since myRIO is based on the Xilinx Zynq chip it uses a different toolchain than previous FPGA devices which may cause the difference in compile/synth times.

-Sam K

LabVIEW Hacker

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