How to find myRIO design analysis?

[JitheshS]

Hi, 

I have a myRIO-1900 and have been writing programs on it. I can't find much information on how a myRIO-1900 works indepth apart from the manual, but what I assume is that the VIs in a program is converted to HDL code which is then synthesised into myRIO. 

I want to know more about the resource usages of the program synthesised and more analysis tools of how the program works. Is there even a way to look at the HDL code in VHDL format which is in the myRIO?  

For example, when you write VHDL code in Vivado, after compiling it will give you a very in-depth analysis of your program (circuit, technically) and useful information such as worst negative slack, etc.

[JitheshS]

Or even, I know in Vivado when I write VHDL code I can also create testbenches to test a program which is a great way of testing if the program works before implementing it on the FPGA board. Are there features like this in the LabVIEW environment?

[MBengths]

Hi JitheshS,

You are right, when you decide to compile your LabVIEW FPGA code your code is converted into HDL and is then compiled onto your FPGA. The articles below describes the LabVIEW FPGA compile process in more detail:

• Understanding the LabVIEW FPGA Compile System (FPGA Module)
• LabVIEW FPGA Compilation Process: From Run Button to Bitfile

During and after the compiling of your code you can generate reports, which provides information about the compilation. You can review different types of device utilization and timing. Here is more information on what you can see in the reports: 

Reports Available from the Compilation Status Window (FPGA Module)

If you don't like to compile before testing your code, you can run your FPGA code in simulation mode directly on the software. This is good for testing and debugging.

Testing and Debugging LabVIEW FPGA Code

If you would like to use some specific features from Vivado to analyze your LabVIEW FPGA code, you can export your FPGA VIs as a Vivado Design Suite Project.

Exporting FPGA VIs as Vivado Design Suite Projects (FPGA Module)

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Best regards,

Marcus Bengths, TSE