FPGA compile error - has no actual or default value

[JussiJii]

Hi

This error is driving me crazy. I can't find any connection to possible design error.

If I add input port, in example like in the picture, next_sample port, I allways get compile error described below:

LabVIEW FPGA:  The compilation failed due to a Xilinx error.

Details:
ERROR: [Synth 8-2029] formal next_sample has no actual or default value [C:/NIFPGA/jobs/BlV6enW_RjFvX56/NiLvFpgaClipContainer.vhd:35]
INFO: [Synth 8-994] next_sample is declared here [C:/NIFPGA/jobs/BlV6enW_RjFvX56/dht22.vhd:37]
INFO: [Synth 8-2810] unit clipcontainer_vhdl ignored due to previous errors [C:/NIFPGA/jobs/BlV6enW_RjFvX56/NiLvFpgaClipContainer.vhd:25]

The wierd thing is, that why compiler doesn't give any errors in example data in port? The diagram how the port is driven is exactly same. I read DIO channel and insert the signal to the port.

Is there some implicit stuff going on behind the scenes what modifies the port so that it is not driven by anything?

Anybody else had this problem?

[JussiJii]

Ok. Now I probably know what was the issue. I had made CLIP node from my VHDL and when I updated VHDL and made the actual IP Integration node, the previously made CLIP was messing the system somehow. I removed CLIP node from the project and synthesis was ok.

[nanocyte]

Just got a similar error. Fortunately the error text was sufficient to tell me that I initialized an array with an empty array. I fixed the size of the array and the error went away

Details:
ERROR: [Synth 8-2029] formal shift_in has no actual or default value [C:/NIFPGA/jobs/mFebjo2_N93TYm9/NiFpgaAG_000000c7_TimedLoopDiagram.vhd:114]
INFO: [Synth 8-994] shift_in is declared here [C:/NIFPGA/jobs/mFebjo2_N93TYm9/NiFpgaShiftReg.vhd:27]
INFO: [Synth 8-2810] unit vhdl_labview ignored due to previous errors [C:/NIFPGA/jobs/mFebjo2_N93TYm9/NiFpgaAG_000000c7_TimedLoopDiagram.vhd:50]

[noar12]

Hello,

I have just run into the same error message and it seems that the problem was in fact an old known issue from 2014 (but I worked with labview FPGA 2017).

http://www.ni.com/product-documentation/52185/en/#474728_by_Category

I had indeed an empty class wired to a shift register and the workaround proposed in the known issue worked great for me