myRIO sequential clip question

[BastiaanO]

Hi,

I have made a CLIP and I am wondering how to implement it.

The vhdl code is used to send data on the falling clock edge and read in data on the falling clock edge.

Sending and receiving takes about 30 clockcycles. The code is based on a state machine and starts sending once an enable signal is given. After transmitting/receiving all bits it returns back to idle.

I read that the CLIP would run even though it is not placed in a loop. However when I make a test vi that has an LED connected to some outputs it seems like it is only runned once? Or  is it actually running but the LED is not updated? I am not sure how to implement is.

Should i use this CLIP in a single cycle time loop? Would it still use the rising and falling edge of the clock? And would it cause problems since it is sequantial and not combinational?

Thank you for your help.

kinds regards,

Bastiaan

[TomTr]

Hi Bastiaan,

Yes the CLIP will constantly run when it is not in a loop, however the LED will only update itself once. Which is the behaviour you have encountered. The link below has a diagram of how to set up the code of this sort:

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_clip_tutor_pass_data/

I don't think the CLIP code will work in a single cycle time loop. This is as as you have said Sending and receiving takes 30 clockcycles and there would be no falling clock edge within the SCTL for the data to be sent and read on.

Let me know if this helps.

Kind regards,

Tom 

[BastiaanO]

Hi Tom, 

Thanks a lot for your help.

However I am still running in some problems. I made two loops to see what is going on. One single cycle loop and one while loop as you suggested.

I added two clip module to the FPGA which i called test1 and test2. The attachment shows my vi.

Hoewever, when i run the code and measuring the outputs with an oscilloscope, only DIO7 seems to give an output, which is 20MHz. DIO0 seems to output a logic 1, DIO1 seems to output 0 and DIO6 seems to output 0 as well. Any idea why this happens? Any tips on how to get the full speed (40 MHz) clock output to work?

As attachments i added the VI and the expected behavior.

The vhdl code:

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity test is
	Port ( 
		clock		: in  STD_LOGIC;
		reset		: in  STD_LOGIC;
		d0		: out STD_LOGIC;
		d1		: out STD_logic
		
	
	);
end test;


architecture Behavioral of test is

signal l1,l2 : std_logic;


begin

	d1 <= clock;
	
	test_proc : process (clock)
		
	begin
		if rising_edge(clock) then
			if reset = '1' then
				l1 <='0';
							
			else
				
				l1<= l1 xor '1';
				
				
				d0 <= l1;
				
			end if;
		end if;
	end process;
		

end Behavioral;

[TomTr]

Hi Bastiaan,

The SCTL does work as it is the only the output of the code which is in the loop. And Digital IO works fine within the loop.

My only thoughts are that this could be caused by timing. The clock for the SCTL is set to default, what value is this? Also what device is this code going onto?

Kind regards,

Tom

[BastiaanO]

I think the main question is how to hook up the CLIP outputs to digital outputs so that it is constantly updated.

How to use both the rising and falling edge?

[BastiaanO]

Hi Tom,

The device is a myRio. And the default clock is 40 MHz.

kind regards,

Bastiaan

[TomTr · Accepted solution]

Hi Bastiaan,

You are reading a 40 MHz signal every 25ns. This means you will be reading the same value of the signal in each iteration so you will always read the same value and you will have a constant output. In order to get a signal of the correct frequency out you need to run the loop with a frequency of at least double the signal. You can create an FPGA derived clock in the way this article describes. Use an 80 MHz clock for the SCTL.

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgahelp/creating_fpga_derived_clk/

Let me know if this helps.

Kind regards,

Tom

[BastiaanO]

Hi Tom,

Thanks a lot.  Using the derived 80MHz clock allows me output a 40MHz clock signal.

So I think with that knowledge I would be able to get my initial send/receive program to work.

kind regards,

Bastiaan