<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Crio and Verilog in General</title>
    <link>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258115#M152</link>
    <description>&lt;P&gt;I have a cRIO 9064,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Can i code the Crio fpga directly in verilog without the use of LabVIEW?&lt;/P&gt;</description>
    <pubDate>Thu, 29 Sep 2022 04:46:57 GMT</pubDate>
    <dc:creator>MusabBinUmair</dc:creator>
    <dc:date>2022-09-29T04:46:57Z</dc:date>
    <item>
      <title>Crio and Verilog</title>
      <link>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258115#M152</link>
      <description>&lt;P&gt;I have a cRIO 9064,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Can i code the Crio fpga directly in verilog without the use of LabVIEW?&lt;/P&gt;</description>
      <pubDate>Thu, 29 Sep 2022 04:46:57 GMT</pubDate>
      <guid>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258115#M152</guid>
      <dc:creator>MusabBinUmair</dc:creator>
      <dc:date>2022-09-29T04:46:57Z</dc:date>
    </item>
    <item>
      <title>Re: Crio and Verilog</title>
      <link>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258189#M153</link>
      <description>&lt;P&gt;LabVIEW RT and LabVIEW FPGA are recommended.&amp;nbsp; What is the reason for not using these tools?&lt;/P&gt;</description>
      <pubDate>Thu, 29 Sep 2022 11:36:06 GMT</pubDate>
      <guid>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258189#M153</guid>
      <dc:creator>Terry_ALE</dc:creator>
      <dc:date>2022-09-29T11:36:06Z</dc:date>
    </item>
    <item>
      <title>Re: Crio and Verilog</title>
      <link>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258527#M154</link>
      <description>&lt;P&gt;Just wanted to teach students verilog and since i had crio, i thought i would show them its working in crio fpga&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 30 Sep 2022 14:21:49 GMT</pubDate>
      <guid>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258527#M154</guid>
      <dc:creator>MusabBinUmair</dc:creator>
      <dc:date>2022-09-30T14:21:49Z</dc:date>
    </item>
    <item>
      <title>Re: Crio and Verilog</title>
      <link>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258563#M155</link>
      <description>&lt;P&gt;I disagree with that approach.&amp;nbsp; The cRIO is made for being programmed (primarily) with LabVIEW RT and LabVIEW FPGA.&amp;nbsp; It will send mixed messages to students.&amp;nbsp; Teaching on a demo board from an FPGA manufacturer is probably better for learning Verilog.&lt;/P&gt;</description>
      <pubDate>Fri, 30 Sep 2022 15:39:47 GMT</pubDate>
      <guid>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258563#M155</guid>
      <dc:creator>Terry_ALE</dc:creator>
      <dc:date>2022-09-30T15:39:47Z</dc:date>
    </item>
    <item>
      <title>Re: Crio and Verilog</title>
      <link>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258571#M156</link>
      <description>&lt;P&gt;Got it. Thank you for replies&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 30 Sep 2022 15:56:35 GMT</pubDate>
      <guid>https://forums.ni.com/t5/General/Crio-and-Verilog/m-p/4258571#M156</guid>
      <dc:creator>MusabBinUmair</dc:creator>
      <dc:date>2022-09-30T15:56:35Z</dc:date>
    </item>
  </channel>
</rss>

