topic Re: Q Encoder in LabVIEW

Q Encoder

Ambrose1464 — Tue, 19 Jul 2016 09:25:20 GMT

I had given a task (picture) about the quadrature encoder. I have problem is how to simulate the A & B signal then using X1 decode?

Your helping is much appreciated.Thank you.

Re: Q Encoder

RavensFan — Tue, 19 Jul 2016 13:43:27 GMT

Please put a little more detail into your question.

First of all, include where LabVIEW fits into your question.

Re: Q Encoder

RTSLVU — Tue, 19 Jul 2016 18:18:10 GMT

Well in simple terms a quadrature encoder outputs two square waves with A or B leading by 90 degrees depending on the direction the encoder is spinning.

Seems trivial to simulate a couple square waves with one of them leading or lagging the other by 90 degrees.

As you can see your X1 output is pulsed once when the leading square wave is high and the lagging is low

Re: Q Encoder

Ambrose1464 — Tue, 19 Jul 2016 23:57:19 GMT

@RTSLVU wrote:
Well in simple terms a quadrature encoder outputs two square waves with A or B leading by 90 degrees depending on the direction the encoder is spinning.

Seems trivial to simulate a couple square waves with one of them leading or lagging the other by 90 degrees.

As you can see your X1 output is pulsed once when the leading square wave is high and the lagging is low

But how i going to draw out the QE at my FPGA target? I need to acquire the channel A and B signal and the counter value from FPGA to Host PC. I totally no idea how to implement out the vi. I'm stuck here.

Re: Q Encoder

Ambrose1464 — Wed, 20 Jul 2016 06:11:22 GMT

@RavensFan wrote:
Please put a little more detail into your question.

First of all, include where LabVIEW fits into your question.

My question is how to implement out the channel A and B signal (either A leading B or B leading A can function both way) after that using X1 decode (this is at FPGA), from the Host PC i want acquire the channel A and B signal and the counter value from the FPGA. Finally display out the signal and the counter value on the Host PC. Currently I still have no idea how I going to generate the channel A and B signal.

Re: Q Encoder

RavensFan — Wed, 20 Jul 2016 13:01:49 GMT

Please give a complete story as to what you are trying to do. Now you are talking about using an FPGA which you failed to mention in the original post.

Where does the FPGA fit into this? Are you trying to take two digital inputs (Chan A and Chan B) into the FPGA then have the FPGA output 3 digital outpus (X1 X2 X4)?

What do you mean by "how to generate channel A and channel B"? Those get generated by your encoder.

Re: Q Encoder

Ambrose1464 — Wed, 20 Jul 2016 13:11:42 GMT

@RavensFan wrote:
Please give a complete story as to what you are trying to do. Now you are talking about using an FPGA which you failed to mention in the original post.

Where does the FPGA fit into this? Are you trying to take two digital inputs (Chan A and Chan B) into the FPGA then have the FPGA output 3 digital outpus (X1 X2 X4)?

What do you mean by "how to generate channel A and channel B"? Those get generated by your encoder.

First i want to sorry about i din mention FPGA. I want to take digital input Channel A and B have 3 digital outputs X1, X2 X4. That I still have problem to build the encoder. No idea how to build out.

Re: Q Encoder

RavensFan — Wed, 20 Jul 2016 13:27:45 GMT

The FPGA has nodes in it that allow it to detect a rising or falling edge. I would set up a loop to detect a rising and falling edge on both Chan A and Chan B. (with a zero timeout)

If any of the 4 are triggered, then you write a true to your X4 output.

If Chan A's rising edge is triggered Chan B is Low OR Chan B's Falling edge is triggered and Chan B is High , then write a true to your X2 output.

If Chan A's rising edge is triggered Chan B is Low, then write a true to X1 output.

Now all of these pulses need to go back to false at some point of time. Do you have a defined pulse width? If so, then have them return to false after X amount of time has passed. But if the encoder is spinning to fast, you could wind up with another trigger point before the pulse has had enough time to remain high. I don't know how you'd handle that. I can only assume the parameters are such that you've specified a limit on how fast the encoder can be.

The pictures seem to give it a 50% duty cycle on X4. But that doesn't seem like it would be accurate because the time between pulses is dependent on the speed of the encoder. I have no idea the best way to handle that.

Re: Q Encoder

RTSLVU — Thu, 18 Jul 2024 20:27:39 GMT

@Ambrose1464 wrote:

First i want to sorry about i din mention FPGA. I want to take digital input Channel A and B have 3 digital outputs X1, X2 X4. That I still have problem to build the encoder. No idea how to build out.

Here is a good place to start Encoder Measurements: How-To Guide

Re: Q Encoder

Ambrose1464 — Thu, 21 Jul 2016 00:07:47 GMT

this is my vi. is it correct? This is my first try. The channel selection means can choose either A lead B or B lead A. Thank you very much.

Re: Q Encoder

Ambrose1464 — Thu, 21 Jul 2016 00:08:04 GMT

@RavensFan wrote:
The FPGA has nodes in it that allow it to detect a rising or falling edge. I would set up a loop to detect a rising and falling edge on both Chan A and Chan B. (with a zero timeout)

If any of the 4 are triggered, then you write a true to your X4 output.

If Chan A's rising edge is triggered Chan B is Low OR Chan B's Falling edge is triggered and Chan B is High , then write a true to your X2 output.

If Chan A's rising edge is triggered Chan B is Low, then write a true to X1 output.

Now all of these pulses need to go back to false at some point of time. Do you have a defined pulse width? If so, then have them return to false after X amount of time has passed. But if the encoder is spinning to fast, you could wind up with another trigger point before the pulse has had enough time to remain high. I don't know how you'd handle that. I can only assume the parameters are such that you've specified a limit on how fast the encoder can be.

The pictures seem to give it a 50% duty cycle on X4. But that doesn't seem like it would be accurate because the time between pulses is dependent on the speed of the encoder. I have no idea the best way to handle that.

this is my vi. is it correct? This is my first try. The channel selection means can choose either A lead B or B lead A. Thank you very much.

Re: Q Encoder

Ambrose1464 — Thu, 18 Jul 2024 20:28:10 GMT

@RTSLVU wrote:

@Ambrose1464 wrote:

First i want to sorry about i din mention FPGA. I want to take digital input Channel A and B have 3 digital outputs X1, X2 X4. That I still have problem to build the encoder. No idea how to build out.

Here is a good place to start Encoder Measurements: How-To Guide

This page need to use hardware is it? I had seen before. First I need to implement an vi first that without hardware and all the input and output function correctly.

Re: Q Encoder

RavensFan — Thu, 21 Jul 2016 01:29:51 GMT

So with this VI you want to GENERATE the signals on the A and B channels.

First glance, I think your boolean logic would work for alternating high and low pulses between the channels.

The flaw in your VI is that you will never write out those trues and falses to the digital outputs. The loop runs forever and the digital outputs are outside of the loop. The boolean values never reaach them. bring the digital outputs into the loop.

Re: Q Encoder

Ambrose1464 — Thu, 21 Jul 2016 01:46:36 GMT

@RavensFan wrote:
So with this VI you want to GENERATE the signals on the A and B channels.

First glance, I think your boolean logic would work for alternating high and low pulses between the channels.

The flaw in your VI is that you will never write out those trues and falses to the digital outputs. The loop runs forever and the digital outputs are outside of the loop. The boolean values never reaach them. bring the digital outputs into the loop.

If i move the digital output inside the loop that mean 1 case have 2 output, i have 2 case total have 4 digital output is it? the 2 case is the A lead B and B lead A. this is my vi. Thank you.

Re: Q Encoder

RavensFan — Thu, 21 Jul 2016 02:14:37 GMT

Do you want to be able to change the channel selection (which I guess actually means direction) while the VI is running? if so, your VI is inside out.

The case structure needs to be inside the loop..

If you move the digital outputs outside the loop, they will never execute because the loop never ends. This is basic dataflow. Do you really want two more digital output channels to be used in teh other case?

Attach a VI instead of pictures, I can then modify it to something that works in a more logical manner.

You can actually merge the last two frames of the sequence structure. You probably don't need the sequence structure at all.

Re: Q Encoder

Ambrose1464 — Thu, 21 Jul 2016 03:37:50 GMT

@RavensFan wrote:
Do you want to be able to change the channel selection (which I guess actually means direction) while the VI is running? if so, your VI is inside out.

The case structure needs to be inside the loop..

If you move the digital outputs outside the loop, they will never execute because the loop never ends. This is basic dataflow. Do you really want two more digital output channels to be used in teh other case?

Attach a VI instead of pictures, I can then modify it to something that works in a more logical manner.

You can actually merge the last two frames of the sequence structure. You probably don't need the sequence structure at all.

Here is my vi. Thanks for your help. I'm really appreciated.

Re: Q Encoder

RavensFan — Thu, 21 Jul 2016 04:09:06 GMT

Here is your VI modified to a more logical structure. It will allow you to change direction while it is operating. Basically be virtually swapping A and B channels in mid-stream, And you are now down to a single set of LED's on the front panel and a single set of digital outputs for channel A and channel B.

Re: Q Encoder

Ambrose1464 — Thu, 21 Jul 2016 04:17:37 GMT

@RavensFan wrote:
Here is your VI modified to a more logical structure. It will allow you to change direction while it is operating. Basically be virtually swapping A and B channels in mid-stream, And you are now down to a single set of LED's on the front panel and a single set of digital outputs for channel A and channel B.

Thanks for your vi . How to implement the x1 decode ? because i want to acquire the signal channel a and b and the counter value from FPGA to pc.

Re: Q Encoder

RavensFan — Thu, 21 Jul 2016 04:33:00 GMT

Look back at what I wrote up in an earlier message.

But I'm confused. You set you wanted to read A and B to generate the X# channels.

Then you post a VI where you are generating A and B signals.

Now you are back to saying you want to acquire A and B signals and generate X1.

I feel like you still haven't clearly told the story of what you are actually trying to do.

Re: Q Encoder

Ambrose1464 — Thu, 21 Jul 2016 05:24:58 GMT

@RavensFan wrote:
Look back at what I wrote up in an earlier message.

But I'm confused. You set you wanted to read A and B to generate the X# channels.

Then you post a VI where you are generating A and B signals.

Now you are back to saying you want to acquire A and B signals and generate X1.

I feel like you still haven't clearly told the story of what you are actually trying to do.

Hi Raven, the final result i want is above diagram. this is what i want the result out. the above diagram will display the result on my host PC.