Measuring capacitance with PXIe-4142 SMU

[Realistic]

Hello,

i am trying to measure capacitance with a SMU. I have made a program where the capacitor is first discharged, then fed a constant current. After a set time i take a voltage measurement, which should reflect the capacitance. The equation is C=i*t/U.

The problem is that the result changes with the source time for some reason. Also the voltage measurement is different from what the oscilloscope shows.

If anyone has any idea on why this is happening please respond

Cheers

[Henrik_Volkers]

Apply rectangular +- current, read voltage hardware timed (more than two points) , apply a LSME fit on the slopes ..

[Realistic]

I dont think its possible to do a hardware timed measurement. There is an option to measure on measure trigger, however i dont know if it would be possible to get time. If you checked how i did it its done by measuring after sourcing. The source phase is 1 second so relative accuracy in time should be sufficent.

The problem is that if i increase source time the measured voltage does not seem to increase linearilly with time (it does seem to be a linear slope on the oscilloscope though).

Also one strange thing i noticed is if i choose a negative voltage as a starting point the measurement goes just completely off.

If you know how do do a better timed measurment or a solution for the non-lineartity problem please do share the procedure to do it with me.

More than 2 points is a viable suggestion.

[Brandon_G.]

Hi Realistic,

Can you provide some more details on how the results change with the source time?  Also what is the expected capacitance and type of capacitor you are measuring?  I had a few thoughts to consider:

1.  "The problem is that if i increase source time the measured voltage does not seem to increase linearilly with time"

Are you sure you're not going into compliance?  If measuring on a scope, you should eventually see the voltage go flat; are you measuring on the SMU before the voltage flatlines?   Also, adding the source delay into your capacitance calculation could be a source of error (though small) since the current source will not instantaneously step from 0 to 10 uA.  You cannot assume that i in your equation C=i*t/U is constant.  I would expect your error to become more neglibile as you increase source delay though.

2. "Also one strange thing i noticed is if i choose a negative voltage as a starting point the measurement goes just completely off."

Can you elaborate?

3. Your 0 volt measurement is being done in the 150 mA range, before switching to the 10 uA range.  Switching in/out shunts on an SMU will inject small amounts of charge that will show up as voltage across your cap.  I would recommend adding another step in your sequence after sourcing 0V/150mA that would source 0uA in the 10uA range and measure your first voltage in this sequence step instead.

4.  10 us of aperture time is small and could add more noise than what's acceptable.  As Henrik_Volkers pointed out you could just measure multiple points and calculate the slope of the line which is your dv/dt.  This will effectively average multiple measurements and even simplifies your math a bit.  You might want to look at the NI-DCPower Measure Step Response.vi example as another way to implement your measurement.  You can take this VI and make it step current instead of voltage and then use the voltage v.s. time graph to calculate your best-fit dv/dt.  As you did before, you'll want to firsts discharge the cap before doing the current step.

Good luck!

[Henrik_Volkers]

As stated you can do a hardware timed voltage and/or current measurement with that device.

RTFM 😉  and have a look at the shipped examples.

Another points to look at:

• If you measure with a scope in parallel you have a 'leakage' resistor of 1Meg in parallel to your C.
• Leakuage of you C
• Soakage of your C (search for 'capacitor soakage')
• Some capacitors have a significant capacity to voltage derating. With increasing voltage the capacity drops down to 50% specified! 

If you can get your hands on on a mica (or slightly less good: foil) capacitor with >60V rating start with theese.

[Realistic]

Hello

I will answer you points by numbers. But first: What i mean results change with source time is if i choose a small source time (for example 1ms) it measures too little. About 10-20% off. At some measurement time the offset goes to 0. Than if i increase the measurement time offset goes positive. At very large measurement times it shows double the expected value. I am measuring a 1uF X7R ceramic capacitor. Its rated at around 60V.

1. I am sure its not going to compliance. Double checked it with oscilloscope. In fact the voltages i am reaching are bellow the half of the range. Adding source delay to measurement if crucial for the measurement itself. While sourcing the capacitor fills up. Current will not step instantaneously, however a large source delay will far overshadow that delay. As you mentioned i use 1 second sourcing time to remove this errors.

2. The slope of the voltage seems to change when going negative. It is rather annoying as i could use double the range if measurement went from -max to +max.

3. Point taken, changed the setup.

4. I chose a small aperture time because the voltage is still changing when measuring and i don't know what actually happens when measuring. I assume multiple measurements are taken and averaged. So a longer aperture time will cause an offset.

I did implement what Henrik_Volkers suggested, it does work better however there is still an offset that varies with measurement time. The offset has gotten smaller though.

I am unable to find the said example. Could you attach it here please?

[Realistic]

As mentioned before i am using a 1uF X7R ceramic capacitor rated at arond 60V, so leakage, soakage and voltage derating should not be a significant factor. The voltage i apply doring measurement is bellow 10V. I will check the example on hardware timing. Hopefully it helps.

[Henrik_Volkers]

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@Realistic wrote:

As mentioned before i am using a 1uF X7R ceramic capacitor rated at arond 60V, so leakage, soakage and voltage derating should not be a significant factor. The voltage i apply doring measurement is bellow 10V. I will check the example on hardware timing. Hopefully it helps.

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For validation I strongly recommend a 1µF foil capacitor. You will find deratings with X7R ceramic SMDs ... (and microphonics,...) 

https://www.maximintegrated.com/en/app-notes/index.mvp/id/5527

https://nepp.nasa.gov/files/25843/2013-Teverovsky-pres-MLCCsBME-n263.pdf

... 'there should not be ...'  is always prone for a surprise 😄  

[Brandon_G.]

In Labview, go to Help--> Find Examples.  Then in the Example Finder navigate to Hardware Input and Output --> Modular Instruments--> NI-DCPOWER (DC Power Supplies)--> NI DCPower Measure Step Response.vi.

I agree with Henric_Volkers that X7R will have a very bad voltage coefficient but perhaps there is other weirdness going on that the voltage/current vs time graphs will give us insight in to.  

[Realistic]

Thank you Henrik_Volkers providing these documentes, they really opened my eyes. I will get a foil capacitor and report back with findings.

Also thanks to Brandon_G for pointing out where to find samples. I was previously searching on the web, and was unable to find samples.

[Realistic · Accepted solution]

So i went and checked the NI DCPower Measure Step Response.vi. sample. Turns out it is a better was to do the mesurment. I measured a 1uF X2 foil capacitor. The measurment is within 1nF of the LC meter measurment, so it works great. In case anyone else needs the same thing i'm providing the VI. Thank you for all your help.

[Brandon_G.]

Just curious, were you able to observe the non-linearities on the X7R with the new VI you created?  Wondering how bad they are or if there may have been something else going on with the previous implementation of the VI.

[Realistic]

Yes, there were still non-linearities on the X7R. They are bad enough to be noticeable on the graph. Also its capacitance slightly changes with the measure voltage.

[Henrik_Volkers]

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@Realistic wrote:

Yes, there were still non-linearities on the X7R. They are bad enough to be noticeable on the graph. Also its capacitance slightly changes with the measure voltage.

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🙂

Some actual data would be nice. There are lies, damn lies, and AD-datasheets .... don't know where the cap datasheets position 😉   Do you have a datasheet for your X7R?  Some already declaire voltage deratings...

So keep in mind: (Arbitary) Assumptions (like should not be, I assume) are AssYouMe 😄 😄

(Shameless hint: Another way to say thank you for a helping message is the KUDOS-button in lower left corner 😉 )

[Realistic]

Unfortunately i do not have a datasheet as i got the capacitor from an unmarked capacitor kit. The strange thing is however that capacitance goes up with the voltage. The capacitor is 1812 in size. 1uF.

Notice the slight nonlinearity in voltage and diviation in current.

Cheers

[Brandon_G.]

The deviation in current is due to being in voltage mode and relying on compliance to drive the output to a (mostly) constant current.  However, this is not the same thing as forcing the output to a constant current in current mode.  The reason for this is that there is a voltage control loop and a current control loop and when you are in compliance the SMU is trying to arbitrate who has control of the loop.  On the other hand, when in current mode (and not near compliance) the current loop has full control of the loop and sets the output to a steady constant current.  I would recommend changing the output to current mode.  You will have to add the Configure Output Function VI to set to current mode as the driver defaults to voltage mode.  You will also have to replace the Level Range, Limit Range and Limit VIs to their current output counterpart.  

It looks like your linearization is across the whole span of voltage but you might (hopefully?) find a more gradual local slope around 0 and a more steeper local slope near the ends. Maybe this could be the issue, but it's hard to tell with a line that's almost straight.  You can subtract the best fit line from the voltage v.s. time line to get a better visual on the non-linearities.  Also, your excitation method is different than how these caps are typically spec'd which uses a small AC signal superimposed on top of a DC signal.  This might not be the issue but it's something to consider when trying to reconcile the measurements with the spec.

[Realistic]

I have considered switching to constant current output, however if i do so it becomes impossible to do a controlled amplitude AC signal on top of a DC signal, as you can only set 1 voltage limit. Also the current diviation is not that bad, its way under 1% and its accounted for in the capacitance calculation. Plus the whole approach with setting 2 voltage points and measuring multiple points in between automatically would be out.

If you look at the first example i provided i had a constant current approach in the beginning and it didn't work. So i conclusion i am happy with the result now and don't think i could do much better even with a high amount of additional time invested.

I have upgraded the VI to use an AC signal on top of a DC signal. I got the AC signal by setting repeat on output. It does become quite difficult to determine when the signal has stabilised when doing so however. As I see no way to set the current limit higher at first (to reach DC offset) without switching to advanced sequence the measurement now takes quite a while (with higher DC offsets). I might try to solve this problem in the future if the need arieses, but right now i don't have time.

[memoryleak]

Should you or anyone else reading this decide to return to measurement improvements, might I suggest a slightly different formula:   Q=CV,  where V is a (smallish) voltage step and Q is the integral of the current sourced into the capacitance.  

The integrating ADCs on the 414x and 4135-4139 SMUs should shine here.  Successive voltage steps may be concatenated to graph C vs V, without the need for a precise slope or worrying about startup/ending conditions as both occur when no current is flowing.

Id suggest the same Measure Step Response VI as an excellent starting point 🙂