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From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
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NI Instruction Sequencer and SPI Example for the NI PXIe-5644/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to issue sequences of SPI commands for hardware-timed DUT control. |
NI I2C Host Example for the PXIe-5644/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the NI I2C IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to implement I2C communication for hardware-timed DUT control.
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NI RFFE Host Example for the PXIe-5644/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to implement RFFE commands for standard specific hardware-timed DUT control. |
NI SPI Host Example for the PXIe-5644/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to issue sequences of SPI commands for hardware-timed DUT control. |
NI Static Digital Host Example for the NI PXIe-5644R/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to implement static digital communication and control. |
Power Servoing Host Example for the NI PXIe-5644R/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, to level the output of an RF power amplifier by iteratively measuring its output power and adjusting the supplied stimulus. |
NI Noise Generation Host Example for the PXIe-5644/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions to adds AWGN to a waveform in real time on the FPGA of a PXIe-5644/45R. The noise is generated using the NI Noise Generation IP. |
NI JTAG Host Example for the PXIe-5644/45R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with JTAG standard signal commands for use in boundary scan testing of ICs and printed circuit boards. |
Streaming Host Example for the NI PXIe-5644R »
This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the Stream Controller IP to stream data from the host VI to the output port of the NI PXIe-5644R as well as from the input port of the NI PXIe-5644R to the host VI. This example also provides a template for setting up peer-to-peer streaming with another device. |
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This IP enables the generation of both uniform and additive white Gaussian (AWGN) noise using an NI LabVIEW FPGA device. |
This IP controls the writing and reading of data to and from FIFOs on the FPGA. |
This IP uses an FPGA-based control loop to rapidly adjust device output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input. |
This IP implements inter-integrated circuit (I2C) communication, including support for both master and slave functionality. |
This IP implements serial peripheral interface (SPI) communication, including support for both master and slave functionality. |
This IP implements MIPI RF front end (RFFE) communication, including support for both master and slave functionality. |