LabVIEW FPGA Idea Exchange

cancel
Showing results for 
Search instead for 
Did you mean: 
Manzolli

Multi-core Compiling

Status: New

Even though ibberger touched the concept in the idea , I do think that most o people uses LabVIEW under Windows environment. Compiling a FPGA VI happens all in the PC under Windows. I noticed that during this process the compiler uses only one core. Since I'm using a machine with a 4 core processor, the CPU use rarely goes above 25%.

 

My idea is to update the compiler allowing it to be multicore. The user should have the option to limit the maximum number of cores available to the compiler. This is necessary because the user may want to continue working, while the compiling process is being done in background.

André Manzolli

Mechanical Engineer
Certified LabVIEW Developer - CLD
LabVIEW Champion
Curitiba - PR - Brazil
42 Comments
T-REX$
Active Participant

It may be dependant on which stage of the compilation you're looking at. If I remember correctly, synthesis (one of the longer stages) is not parallelized, but Place & Route is.

Cheers!

TJ G
jbeale1
Member

T-REX$: You are correct. I'm running a compile now and I had been watching the 25% CPU during synthesis. It has now reached "Placing" and just as you say, the vivado.exe process CPU use goes over 90% at times.  In the smaller project that I originally posted about, the "Placing" and "Routing" phases were so short I didn't notice the change in CPU use.

labviewman
Member

I have looked around for this bit of info but I didn't see it posed anywhere so I thought I should share what I have found.

 

I develop/debug in VMware Workstation because I can install any software I want and not get IT involved (host computer is totally locked down) which would take 4-6 weeks to get approval to install anything on the host OS.  I have discovered that with the virtual machine configured for only one processor, my FPGA compile times are about 22%-30% LESS than if compiled on the host OS.  I tried this with simple code (compile time of 13 minutes, reduced by 3.65 minutes) and somewhat more complex code (compile time of 26 minutes, saved 10.9 minutes).

 

Here is some config info:

VM: WinXP SP3, 1 processor, 3.2 GBytes RAM

Host OS: Windows 7 Enterprise, 32 GBytes of RAM, i7 processor (4910MQ, quad core hyper-threaded CPU at 3.9 GHz in turbo mode)

LabVIEW 2014

 

I'm not 100% sure, but I believe I had similar reductions in compile times with the Win7 as the OS in the VM.

 

Has anyone else tried this?

Intaris
Proven Zealot

It has to do with thread swapping on WIndows slowing the process down on multiple cores (something Linux manages a lot better - therefore the linux compiles are a bit faster)

 

You can limit the CompileWorker.exe to 1 core on your native PC and it will then also compile faster.  I have limited mine to 1 core and my FPGA compiles are much faster.

labviewman
Member

I figured it had to do with constant thread swapping and managing multiple cores.  I did see a post on how to configure what you are saying (I think it was this thread) but haven't tried it yet.

 

I wonder why NI doesn't do this as a default...

FyrewurX
Member

can I implement this method in my Virtual Machine running an XP for compilation? My host OS is win8.1 with core i7, 4GB RAM and it does have a problem in compilation so i had to use VM.

labviewman
Member

Yes.  Only give 1 CPU to the VM.

cgibson
Member

Hi folks!

 

I sat down and tried Lorn's method on a Windows 7 box (direct not VM) with LabVIEW 2014 SP1. Before I tried it I checked that Turbo Boost was available and enabled on my machine.

My 1 hour and 20 minute compile went to 5 hours and 31 minutes. FWIW, this was with the Xilinx Vivado 2013.4 (63-bit).

 

I am thinking that Crossrulz is correct, he usually is, and that now Lorn's fix actually puts you at a disadvantage.

labviewman
Member

I tried Lorn's method, which gave the same result as my suggestion of only using 1 CPU in the VM and had the following results (in a VM):

 

1 CPU: 10 min 47 seconds

2 CPUs: 14 min

 

Granted, the FPGA code is pretty simple (the FPGA is a Virtex-5 LX50), but 1 CPU works great for the 'older' FPGAs.

 

Intaris
Proven Zealot

I think the 1 CPU ruls can only be reliably applied to the ISE compiler.  Vivado has a lot of parallel compiling optimisations in there AFAIK and willmost likely benefit a lot from multiple cores.