CompactRIO Waveform Library

[LeifS]

OK, I understand that there is no benefit of using timed loops i this case for control of the timing, but my point was rather to achive a higer priority in relation to other RT tasks, in my case writing to a TDMS file on flashdrive via nondeterministic USB.

I agree that timed loops tend to make this solution overcomplex - there seems to be no good way of setting the loop period time other than "too short" and accept "finished late" on each loop execution? (Otherwise the DMA FIFO will eventually get overflow'ed).

So the best bet is to put the Host DMA read into a higer priority SubVI, or do you believe this is unnessecary?

[bww]

Hi Jeff,

I am syncing the cRIO to an NTP server periodically and every time that I have checked the cRIO's time it appears to be spot on. I understand that each clock will drift a bit and at different rates however 10-20 minutes seems excessive, which is why I'm so confused. Do you think that by not resetting the time stamp each read the error could grow this large? I'm not looking for mSec resolution, I need +/- 5 sec.

LeifS,

I see what your talking about with the IRQ, I miss-unerstood the FPGA section.

Regards,

bw

[Jeff_T.]

LeifS,

I still believe the timed loop is unnecessary.  If you want to give the read loop priority because the CPU usage is very high, then I would say you have other problems on your hands.  If you want to give it priority because multiple processes are sharing one CPU resource, then I would say that is what the buffer is for. 

bww,

Tell me more about the 10-20min thing.  The first block that is read should equal the cRIO system time.  Over a long period of time the timestamps could drift and if left running is no limit to how far those timestamps could offset.  Is this the behavior you are seeing or are things seriously offset even from the first block read?

Regards,

Jeff 

[bww]

Jeff,

I suspect the time error is growing, however the system is in the field now and not immediately accesible. I will try and maks some changes tonight, with the First Read concept and see what happens.

Thanks for the advice.

bw

[bww]

Jeff & LeifS,

I changed my application to have the "First Read" flag always be true and now my timestamps align. Thank you both for your comments!

Regards,

Bryan

[minnellac]

You've mentioned a delay on file creation a few times here. There is a known issue with the filesystem on the crio that leads to this behaviour. The problem is much worse on an attached USB flash drive (Reliance or FAT32). The bottom line is, keep the number of files in a directory below 700 on a FAT32 formatted USB stick. Above that, it can takes 10's of seconds to open/create a file in a directory.

The problem is alluded to in this thread:

http://forums.ni.com/t5/LabVIEW-Real-Time-Idea-Exchange/Add-Reliance-NITRO-to-the-list-of-supported-...

Chris

[BrainDrain]

 I wonder if the "FPGA Waveform Acquisition and Logging on CompactRIO" - template (not library) on the can be used for devices with a fixed sampling rate ... or which vis / type definitions etc have to be adepted in order to use them... 

I tried to use the FPGA WAaLoCRIO-Template Project for my first steps in FPGA-Programming but was stucked trying to adapt the template to my hardware because my NI9215 analog in module did no support the "set sampling rate"or the "start" and "stop" option. It was not a big deal to modify the FPGA Vi, but unvortionately the  missing "acquistion time " option also spoiled VIs on a higher level like the "Start Acquisition and Logging.vi" where the "FPGA VI Reference Out" seems to be broken. What has to be changed in order to get it up and running? Now, I am using the Waveform Reference Library. But it would be nice to be able to use the project template as provided at the LV2012 start-up screen.

Best wishes,

Luke

LV 2012 f1; cRIO 9022 + 9114 Chassis (Virtex 5 LX50 FPGA), Modules: NI 9215; NI 9263; NI 9401

PS: I am not sure if this is the right place to post  - because I am not sure if you refer to the Reference Library or to the Waveform Reference Project template ...

[Christian_L]

Luke,

Thank you for your feedback. You are correct that this discussion forum is intended for the cRIO Waveform Reference Library, and not the Project Template in LV 2012. However, the project template was designed by the same engineers and is based on the same general principles. I will forward your feedback to the appropriate groups within NI.

In the future please post feedback and comments in the general LabVIEW discussion forums and thank you again for taking the time to provide your feedback.

When you adapt the template to to use the 9215 module, make sure you add some timing on the FPGA to control the acquisition rate. The 9215 will perform an acquisition whenever the I/O node for the module is called, so the loop timing of the Acquisition Loop controls the acquisiton rate in this case.

If you remove any of the front panel controls on the Main FPGA VI as part of your changes, you will need to make the corresponding change in the RT VIs that interface to the FPGA VIs (Start Acquisition and Logging.vi on RT). For example, if you remove the Data Rate control on the FPGA, you need to remove the Read/Write node that writes to that control in the RT VI. However I would not remove this particular control, but repurpose it to control the loop timting of the Acquisition Loop on the FPGA.  Somewhere (probably in RT) you will need to convert Data Rate (Hz) to loop period (ms or us) since the loop timing functions on the FPGA expect an input of time, not frequency.

[BrainDrain]

Hi Christian!

Thank you very much for your reply! 

> When you adapt the template to to use the 9215 module, make sure you add some timing on the FPGA to control the acquisition rate. The 9215 will perform an acquisition whenever the I/O node for the module is called, so the

> loop  timing of the Acquisition Loop controls the acquisiton rate in this case.

But this would mean if I would like to use the highest rate possible  I do not have to provide this info ... right? 

>If you remove any of the front panel controls on the Main FPGA VI as part of your changes, you will need to make the corresponding change in the RT VIs that interface to the FPGA VIs (Start Acquisition and Logging.vi on RT). >For example, if you remove the Data Rate control on the FPGA, you need to remove the Read/Write node that writes to that control in the RT VI. However I would not remove this particular control, but repurpose it to control the >loop timting of the Acquisition Loop on the FPGA.  Somewhere (probably in RT) you will need to convert Data Rate (Hz) to loop period (ms or us) since the loop timing functions on the FPGA expect an input of time, not frequency.

Ok, that is the easy part ...  

Because I have also a question regarding the cRIO-WRA-LIBRARY I will  start add a new reply... to this thread.

Best wishes and thanks again for the response,

Luke

[BrainDrain]

 Hi everybody!

I have problems using the examples. After adapting the examples (FPGA-target for NonDeltaSig) to my hardware and update the FPGA-Vi reference in the RT-example for contious acquisiton, I do get two erros:

1. Details Display Dialog.vi --> Get Help Wndow Status: Function is not supported for current target

2. Not Found Dialog.vi  --> Control Online Help: Function not supported for current target

    SubVi 'Three Button Dialog.vi' : Sub Vi not supported in current target

Any ideas what to do? It might be trivial - but I am a complete novice to Realtime, cRIO and FPGA.

Many thanks in advance,

Luke